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EP1C12F100C6ES Datasheet(PDF) 51 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 51 Page - Altera Corporation |
51 / 104 page ![]() Altera Corporation 2–45 January 2007 Preliminary I/O Structure Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration The Cyclone device IOE includes programmable delays to ensure zero hold times, minimize setup times, or increase clock to output times. A path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays Chip-Wide Reset OE Register VCCIO Optional PCI Clamp Column or Row Interconect ioe_clk[5..0] Input Register Input Pin to Input Register Delay or Input Pin to Logic Array Delay Input Pin to Logic Array Delay Drive Strength Control Open-Drain Output Slew Control sclr/preset OE clkout ce_out aclr/prn clkin ce_in Programmable Pull-Up Resistor Bus Hold PRN CLRN DQ Output Register PRN CLRN DQ PRN CLRN DQ VCCIO comb_datain data_in ENA ENA ENA Output Pin Delay |
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