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PIC12F683 Datasheet(PDF) 16 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 16 Page - Microchip Technology |
16 / 148 page PIC12F683 DS41211B-page 14 Preliminary 2004 Microchip Technology Inc. 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE bit 7 bit 0 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt bit 2 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 1 TMR2IE: Timer 2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer 2 to PR2 match interrupt 0 = Disables the Timer 2 to PR2 match interrupt bit 0 TMR1IE: Timer 1 Overflow Interrupt Enable bit 1 = Enables the Timer 1 overflow interrupt 0 = Disables the Timer 1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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