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PIC12F683 Datasheet(PDF) 12 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 148 page  PIC12F683 DS41211B-page 10 Preliminary 2004 Microchip Technology Inc. TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOD Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 83 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 83 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 83 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 83 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 83 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 83 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 83 8Ch PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 83 8Dh — Unimplemented — — 8Eh PCON — — ULPWUE SBODEN — —POR BOD --01 --qq 16, 83 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 x000 28, 83 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 23, 83 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 45, 83 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU(3) — —WPU5 WPU4 — WPU2WPU1WPU0 --11 -111 32, 83 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 33, 83 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN —VRR — VR3 VR2 VR1 VR0 0-0- 0000 53, 83 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 65, 83 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 65, 83 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 66, 84 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 66, 84 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 57, 84 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 59, 84 Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: OSCCON<OSTS> bit reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator. 3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. |
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