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PIC12F683 Datasheet(PDF) 9 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 148 page  2004 Microchip Technology Inc. Preliminary DS41211B-page 7 PIC12F683 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC12F683 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Regis- ters (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are general purpose registers, implemented as static RAM. Register loca- tions F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 (Status<5>) is the bank select bit. •RP0 = 0: Bank 0 is selected •RP0 = 1: Bank 1 is selected 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). PC<12:0> 13 000h 0004 0005 07FFh 0800h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 Note: The IRP and RP1 bits (Status<7:6>) are reserved and should always be maintained as ‘0’s. |
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