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PIC12F683 Datasheet(PDF) 87 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 87 Page - Microchip Technology |
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87 / 148 page  2004 Microchip Technology Inc. Preliminary DS41211B-page 85 PIC12F683 12.4 Interrupts The PIC12F683 has 11 sources of interrupt: • External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • CCP Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: • INT Pin Interrupt • GPIO Change Interrupt • TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: • EEPROM Data Write Interrupt • A/D Interrupt • 2 Comparator Interrupts • Timer1 Overflow Interrupt • Timer 2 Match Interrupt • Fail-Safe Clock Monitor Interrupt • CCP Interrupt When an interrupt is serviced: • The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. For additional information on Timer1, Timer2, comparators, A/D, data EEPROM or CCP modules, refer to the respective peripheral section. 12.4.1 GP2/INT INTERRUPT External interrupt on GP2/INT pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The GP2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 12.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 12-10 for timing of wake-up from Sleep through GP2/INT interrupt. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. Note: The ANSEL (91h) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. |
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