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PIC12F683 Datasheet(PDF) 81 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 81 Page - Microchip Technology |
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81 / 148 page  2004 Microchip Technology Inc. Preliminary DS41211B-page 79 PIC12F683 12.3.1 POWER-ON RESET The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply con- nect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 “Electrical Specifica- tions” for details. If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches VBOD (see Section 12.3.4 “Brown-out Detect (BOD)”). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option. FIGURE 12-2: RECOMMENDED MCLR CIRCUIT 12.3.3 POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Detect. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.4 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A config- uration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Detect is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: •VDD variation • Temperature variation • Process variation See DC parameters for details (Section 15.0 “Electrical Specifications”). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 µs. VDD PIC12F683 MCLR R1 1k Ω (or greater) C1 0.1 µF (optional, not critical) |
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