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PIC12F683 Datasheet(PDF) 63 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 63 Page - Microchip Technology |
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63 / 148 page  2004 Microchip Technology Inc. Preliminary DS41211B-page 61 PIC12F683 9.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Ana- log Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4. The maximum recommended impedance for analog sources is 10 k Ω. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9- 1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). EQUATION 9-1: ACQUISITION TIME FIGURE 9-4: ANALOG INPUT MODEL Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k Ω. This is required to meet the pin leakage specification. TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC = TCOFF = 2 µs + TC + [(Temperature – 25°C)(0.05 µs/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = -120 pF (1 k Ω + 7 kΩ +10 kΩ) In(0.0004885) = 16.47 µs TACQ = 2 µs + 16.47 µs + [(50°C – 25°C)(0.05 µs/°C)] = 19.72 µs CPIN VA RS ANx 5 pF VDD VT = 0.6V VT = 0.6V ILEAKAGE RIC ≤ 1k Sampling Switch SS RSS CHOLD = DAC capacitance VSS 6V Sampling Switch 5V 4V 3V 2V 567 8 9 10 11 (k Ω) VDD = 120 pF ± 500 nA Legend:CPIN VT ILEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance (from DAC) various junctions |
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