PIC12F683 datasheet(53/148 Pages) MICROCHIP

Part #	PIC12F683

Description	8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

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Manufacturer	MICROCHIP [Microchip Technology]

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 2004 Microchip Technology Inc.

Preliminary

DS41211B-page 51

PIC12F683

8.4

Comparator Output

The comparator output is read through the CMCON0

register. This bit is read-only. The comparator output

may also be directly output to the GP2 pin. When

enabled, multiplexors in the output path of the GP2 pin

will switch and the output will be the unsynchronized

output of the comparator. The uncertainty of the

comparator is related to the input offset voltage and

the response time given in the specifications.

Figure 8-4 shows the output block diagram for the

comparator.

The TRISIO bit will still function as an output enable/

disable for the GP2 pin while in this mode.

The polarity of the comparator outputs can be changed

using the CINV bit (CMCON0<4>).

Timer1 gate source can be configured to use the T1G

pin or the comparator output as selected by the T1GSS

bit (CMCON1<1>). This feature can be used to time the

duration or interval of analog events. The output of the

comparator can also be synchronized with Timer1 by

setting

the

CMSYNC

bit

(CMCON1<0>).

When

enabled, the output of the comparator is latched on the

falling edge of the Timer1 clock source. If a prescaler is

used with Timer1, the comparator is latched after the

prescaler. To prevent a race condition, the comparator

output is latched on the falling edge of the Timer1 clock

source and Timer1 increments on the rising edge of its

clock source. See Figure 8-4, Comparator Output

Block

Diagram

and

Figure 6-1,

Timer1

on

the

PIC12F683 Block Diagram for more information.

It is recommended to synchronize the comparator with

Timer1 by setting the CMSYNC bit when the compara-

tor is used as the Timer1 gate source. This ensures

Timer1 does not miss an increment if the comparator

changes during an increment.

8.5

Comparator Interrupt

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bit, as read from CMCON0<6>, to

determine the actual change that has occurred. The

CMIF bit (PIR1<3>) is the Comparator Interrupt Flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a ‘1’ to this register, a

simulated interrupt may be initiated.

The

CMIE

bit

(PIE1<3>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a)

Any read or write of CMCON0. This will end the

mismatch condition.

b)

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON0 will end the mismatch condition and

allow flag bit CMIF to be cleared.

Note:

If a change in the CMCON0 register

(COUT)

should occur

when

a

read

operation is being executed (start of the

Q2 cycle), then the CMIF (PIR1<3>)

interrupt flag may not get set.

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