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PIC12F683 Datasheet(PDF) 34 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 34 Page - Microchip Technology |
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34 / 148 page  PIC12F683 DS41211B-page 32 Preliminary 2004 Microchip Technology Inc. REGISTER 4-2: TRISIO – GPIO TRI-STATE REGISTER (ADDRESS: 85h) REGISTER 4-3: WPU – WEAK PULL-UP REGISTER (ADDRESS: 95h) U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> reads ‘1’ in XT, LP and HS modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. 4: WPU<5:4> reads ‘1’ in XT, LP and HS modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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