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PIC12F683 Datasheet(PDF) 29 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 29 Page - Microchip Technology |
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29 / 148 page  2004 Microchip Technology Inc. Preliminary DS41211B-page 27 PIC12F683 3.7 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. FIGURE 3-8: FSCM BLOCK DIAGRAM The FSCM function is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). It is applicable to all external clock options (LP, XT, HS, EC, RC or IO modes). In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR1<2>) and generate an oscillator fail interrupt if the OSFIE bit (PIE1<2>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automati- cally cleared to reflect that the internal oscillator is active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit. The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 3-8 shows the FSCM block diagram. On the rising edge of the sample clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the sample clock occurs and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscil- lator is enabled when FSCM is enabled, as reflected by the IRCF. 3.7.1 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 3-9: FSCM TIMING DIAGRAM Primary LFINTOSC ÷ 64 Oscillator Clock Clock Fail Detector Clock Failure Detected Note: Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled. Note: Primary clocks with a frequency ≤ ~488 Hz will be considered failed by the FSCM. A slow starting oscillator can cause an FSCM interrupt. OSCFIF CM Output System Clock Output Sample Clock Failure Detected Oscillator Failure Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. (Q) CM Test CM Test CM Test |
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Similar Description - PIC12F683 |
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