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PIC12F683 Datasheet(PDF) 26 Page - Microchip Technology |
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PIC12F683 Datasheet(HTML) 26 Page - Microchip Technology |
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26 / 148 page  PIC12F683 DS41211B-page 24 Preliminary 2004 Microchip Technology Inc. 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the system clock source (SCS = 1), or when any of the following are enabled: • Two-Speed Start-up (IESO = 1 and IRCF = 000) • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not. 3.4.4 FREQUENCY SELECT BITS (IRCF) The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: •8 MHz • 4 MHz (Default after Reset) •2 MHz •1 MHz • 500 kHz • 250 kHz • 125 kHz •31 kHz 3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10 µs delay after the IRCF bits are modified before the fre- quency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. IRCF bits are modified. 2. If the new clock is shut down, a 10 µs clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. CLKOUT is now connected with the new clock. HTS/LTS bits are updated as required. 6. Clock switch is complete. If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. 3.5 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit. 3.5.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals. • When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). • When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared. Note: Following any Reset, the IRCF bits are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail- Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source. |
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