Clock operation

M41T81

20/30

3.8

Output driver pin

When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the

IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the

Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h

are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.

Note:

The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.

3.9

Preferred initial power-on default

Upon initial application of power to the device, the following register bits are set to a '0' state:

Watchdog Register; AFE; ABE; SQWE; and FT. The following bits are set to a '1' state: ST;

OUT; and HT (see Table 5 on page 20).

Table 5.

Preferred default values

Condition

ST

HT

Out

FT

AFE

SQWE

ABE

WATCHDOG

1.

BMB0-BMB4, RB0, RB1.

2.

State of other control bits undefined.

111

00

0

0

0

Subsequent power-up (with

3.

UC = unchanged

UC

1

UC

0

UC

UC

UC

0