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CS5535-UDC Datasheet(PDF) 67 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 67 Page - National Semiconductor (TI) |
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67 / 555 page  Revision 0.8 67 www.national.com Global Concepts and Features (Continued) 3.8 STANDARD GEODELINK DEVICE MSRS All GeodeLink Devices have the following Standard MSRs and are always located at the addresses indicated below from the base address given in Table 3-2 "CS5535 MSR Addresses from GX2 Processor" on page 54: • MSR Address 0: GeodeLink Device Capabilities (GLD_MSR_CAP) • MSR Address 1: GeodeLink Device Master Configura- tion (and GLA Prefetch) (GLD_MSR_CONFIG) • MSR Address 2: GeodeLink Device System Manage- ment Interrupt Control (GLD_MSR_SMI) • MSR Address 3: GeodeLink Device Error Control (GLD_MSR_ERROR) • MSR Address 4: GeodeLink Device Power Management (GLD_MSR_PM) • MSR Address 5: GeodeLink Device Diagnostic MSR (GLD_MSR_DIAG) (This register is reserved for internal use by National and should not be written to.) 3.8.1 MSR Address 0: Capabilities The Capabilities MSR (GLD_MSR_CAP) is read only and provides identification information as illustrated Table 3-7. 3.8.2 MSR Address 1: Master Configuration The defined fields in the GeodeLink Device Master Config- uration MSR (GLD_MSR_CONF) vary depending upon the device. Refer to the appropriate GeodeLink Device register chapter starting in Section 5.0 "Register Descriptions" on page 184. 3.8.3 MSR Address 2: SMI Control Each GeodeLink Device within the CS5535 incorporates System Management Interrupts (SMIs). These SMIs are controlled via the Standard GLD_MSR_SMI located at MSR Address 2 within each GLD (see Table 3-8). The lower 32 bits of this register contain Enable (EN) bits, while the upper 32 bits contain Flag (FLAG) bits. The EN and FLAG bits are organized in pairs of (n, n+32). For example: (0,32); (1,33); (2,34); etc. The GLD_MSR_SMI is used to control and report events. An event is any action or occurrence within the GeodeLink Device requiring processor attention. The FLAG bits are status bits that record events. The EN bits enable events to be recorded. An EN bit must be 1 for an event to be recorded (with the exception of the GLUI and the GLCP - the EN bit must be 0 for an event to be recorded). When an event is recorded, the associated FLAG bit is set to a 1. SMI events are of two types: Asynchronous SMI (ASMI) and Synchronous SMI (SSMI). Table 3-7. GLD_MSR_CAP Bit Descriptions Bit Name Description 63:24 RSVD Reserved. Reads as 0. 23:8 DEV_ID Device ID. Identifies the module. 7:0 REV_ID Revision ID. Identifies the module revision. Table 3-8. Standard GLD_MSR_SMI Format 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7654321 0 |
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