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CS5535-UDC Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 555 page  www.national.com 14 Revision 0.8 Architecture Overview (Continued) 1.6.2 Programmable Interval Timers - Legacy Timers The Programmable Interval Timer (PIT) generates pro- grammable time intervals from the divided clock of an external clock input. The PIT is an 8254-style timer that contains three 16-bit independently programmable counters. A 14.318 MHz external clock signal (from a crys- tal oscillator or a clock chip) is divided by 12 to generate 1.19 MHz for the clocking reference of all three counters. 1.6.3 Programmable Interrupt Controller - Legacy Interrupt The Programmable Interrupt Controller (PIC) consists of two 8259A-compatible programmable interrupt controllers connected in cascade mode through interrupt number two. Request mask capability and edge-level controls are pro- vided for each of the 15 channels along with a 15-level pri- ority controller. An IRQ mapper takes up to 62 discrete interrupt request (IRQ) inputs and maps or masks them to the 15 PIC inputs and to one ASMI (asynchronous system management interrupt). All 62 inputs are individually maskable and sta- tus readable. In addition to the above 8259A features, there are shadow registers to obtain the values of legacy 8259A registers that have not been historically readable. 1.6.4 Keyboard Emulation Logic - Legacy Support Interface The PS2 Keyboard Emulation Logic (KEL) provides a vir- tual 8042 keyboard controller interface that may be used to map non-legacy keyboard and mouse sources to this tradi- tional interface. Flexible keyboard emulation logic allows PS2 keyboard emulation traditionally used for USB legacy keyboard emulation. For example, USB sources may be ‘connected’ to this interface via SMM (System Manage- ment Mode) software. It also allows mixed environments with one LPC legacy device and one USB device. 1.6.5 Universal Asynchronous Receiver Transmitter and IR Port Two Universal Asynchronous Receiver Transmitters (UARTs) provide a system interface to the industry stan- dard serial interface consisting of the basic transmit and receive signals. One of the UARTs can be coupled with infrared logic and be connected to an infrared sensor. The UARTs are both 16550A and 16450 software-compati- ble and contain shadow register support for write-only bit monitoring. The ports have data rates up to 115.2 kbps. Serial port 1 can be configured as an infrared communica- tions port that supports Sharp-IR, Consumer-IR, and HP- SIR as well as many popular consumer remote-control pro- tocols. 1.6.6 System Management Bus Controller The System Management Bus (SMB) Controller provides a system interface to the industry standard SMB. The SMB allows easy interfacing to a wide range of low-cost memory and I/O devices, including: EEPROMs, SRAMs, timers, ADC, DAC, clock chips, and peripheral drivers. These lines are shared with two GPIOs and must be configured as SMB ports in order for this interface to be functional. The SMB is a two-wire synchronous serial interface com- patible with the System Management Bus physical layer. The SMB Controller can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. As a slave device, the SMB Controller may issue a request to become the bus master. 1.6.7 Low Pin Count Port This port provides a system interface to the industry stan- dard Low Pin Count (LPC) bus. The controller can convert an internal Local bus memory or I/O cycle to an external LPC cycle. It receives serial IRQs from the LPC and con- verts them to parallel form so they can be routed to the IRQ mapper. Lastly, it interacts with Legacy DMA logic to per- form DMA between on-chip or off-chip DMA devices. The LPC interface is based on the Intel’s Low Pin Count (LPC) Interface specification v1.0. In addition to the required signals/pins specified in the Intel specification, it also supports two optional signals: • LPC_DRQ# - LPC DMA Request • LPC_SERIRQ - LPC Serial encoded IRQ The LPC interface supports memory, I/O, DMA, and Intel’s firmware hub interfaces. 1.6.8 General Purpose I/Os with Input Conditioning Functions (ICF) There are 32 GPIOs in the CS5535, 28 are externally avail- able, that offer a variety of user-selectable configurations including accessing auxiliary functions within the chip, and input conditioning such as debounce and edge detect. Register access is configured in such a way as to avoid Read-Modify-Write operations; each GPIO may be directly and independently configured. Several groups of GPIOs are multiplexed between the LPC Controller, the SMB Controller, access to the UARTs and MFGPTs, and power management controls including sys- tem power and Sleep buttons. Six of the GPIOs are in the Standby power domain, giving them increased versatility as wakeup event sources when only Standby power is applied. A GPIO interrupt and power management event (PME) mapper can map any subset of GPIOs to the PICs (eight interrupts available) or Power Management Subsystem (eight events available). |
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