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CS5535-UDC Datasheet(PDF) 97 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535-UDC
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535-UDC Datasheet(HTML) 97 Page - National Semiconductor (TI)

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DIVIL Functional Description (Continued)
•Standard MSRs - Includes the Standard GeodeLink
Device MSRs found in all GeodeLink Devices: Capabili-
ties, Master Configuration, SMI Control, Error Control,
Power Management, and Diagnostics.
• Local BARs - Local Base Address Registers (LBARs)
establish the location of non-legacy functions within the
Diverse Device. The module also includes logic to
compare the current bus cycle address to the LBAR to
detect a hit. For the I/O LBARs, the I/O address space
000h-4FFh is off limits. No I/O LBAR is allowed to point
to this space.
• Data Out Mux (DOM) - This mux is not explicitly illus-
trated. Each function above produces a single output to
the DIVIL. The DIVIL DOM has a port for each of the
functions and is responsible for selecting between them.
4.6.1
LBARs and Comparators
The LBARs are used to establish the address and hence,
chip select location of all functions that do not have fixed
legacy addresses. This block also has comparators to
establish when a current bus cycle address hits an LBAR.
A hit is passed to the address decode block and results in a
chip select to the target device if there are no conflicts. The
mask and base address values are established via an
MSR.
4.6.1.1
Fixed Target Size I/O LBARs
This discussion applies to the following LBARs:
• MSR 51400008h: IRQ Mapper (MSR_LBAR_IRQ)
• MSR 5140000Bh: SMB (MSR_LBAR_SMB)
• MSR 5140000Ch: GPIO and ICFs (MSR_LBAR_GPIO)
• MSR 5140000Dh: MFGPTs (MSR_LBAR_MFGPT)
• MSR 5140000Eh: ACPI (MSR_LBAR_ACPI)
• MSR 5140000Fh: Power Management Support
(MSR_LBAR_PMS)
The IO_MASK only applies to the upper bits [15:12] (see
Figure 4-11). Normally, one would set all the mask bits (i.e.,
no mask on upper bits). One should only mask or clear bits
if address wrapping or aliasing is desired.
•Rule. When a mask bit is cleared, the associated bit in
the base address must also be cleared. Otherwise, the
compare will not be equal on these bits. This rule
applies to both memory and I/O LBARs.
The base size is fixed based on the target. For example,
the GPIO takes 256 bytes of address space. Therefore, the
base only applies to bits [15:8]. Base bits [7:0] are always
cleared by the hardware. Therefore, the base is always
forced by hardware to be on a boundary the size of the tar-
get.
Figure 4-11. I/O Space LBAR - Fixed Target Size
ADDR[15:12]
I/O_MASK
Compare
BASE_ADDR
Hit
[15:n]
[15:12]
Notes:
1)
The I/O mask is always 4 bits.
2)
The I/O base address is variable ([15:n]).
The value of “n” depends on the I/O space requirements of the target. For example, a device needing 4, 8, 16, 32,
64, 128, or 256 bytes of I/O space has “n” = 2, 3, 4, 5, 6, 7, 8, respectively. The value “n” for various functions is:
MSR_LBAR_IRQ
n = 5
MSR_LBAR_SMB
n = 3
MSR_LBAR_GPIO
n = 8
MSR_LBAR_MFGPT
n = 6
MSR_LBAR_ACPI
n = 5
MSR_LBAR_PMS
n = 7
MSR_LBAR_FLASH_IO
n = 4


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