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CS5535-UDC Datasheet(PDF) 92 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 92 Page - National Semiconductor (TI) |
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92 / 555 page  www.national.com 92 Revision 0.8 ATAC Functional Description (Continued) 4.4.2.3 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 4-8. When the bus master is enabled (Com- mand register bit 0 = 1), data transfer proceeds until each PRD in the PRD table has been transferred. The bus mas- ter does not cache PRDs. The PRD table consists of two DWORDs. The first DWORD contains a 32-bit pointer to a buffer to be transferred. This pointer must be 4-byte aligned. The second DWORD con- tains the size (16 bits) of the buffer and the EOT (End Of Table) flag. The size must be in multiples of 1 WORD (2 bytes) or zero (which means a 64 kB transfer). The EOT bit (bit 31) must be set to indicate the last PRD in the PRD table. 4.4.2.4 Programming Model The following steps explain how to initiate and maintain a bus master transfer between memory and an IDE device: 1) Software creates a PRD table in system memory. Each PRD entry is 8 bytes long, consisting of a base address pointer and buffer size. The maximum data that can be transferred from a PRD entry is 64 kB. A PRD table must be aligned on a 4-byte boundary. The last PRD in a PRD table must have the EOT bit set. 2) Software loads the starting address of the PRD table by programming the PRD Table Address register. 3) Software must fill the buffers pointed to by the PRDs with IDE data. 4) Write 1 to the Bus Master Interrupt bit and Bus Master Error (Status register bits 2 and 1) to clear the bits. 5) Set the correct direction to the Read or Write Control bit (Command register bit 3). Engage the bus master by writing a 1 to the Bus Mas- ter Control bit (Command register bit 0). The bus master reads the PRD entry pointed to by the PRD Table Address register and increments the address by 08h to point to the next PRD. The transfer begins. 6) The bus master transfers data to/from memory responding to bus master requests from the IDE device until all PRD entries are serviced. 7) The IDE device signals an interrupt once its pro- grammed data count has been transferred. 8) In response to the interrupt, software resets the Bus Master Control bit in the Command register. It then reads the status of the controller and IDE device to determine if the transfer is successful. Table 4-8. Physical Region Descriptor Format DWORD Byte 3 Byte 2 Byte 1 Byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Memory Region Physical Base Address [31:4] (IDE Data Buffer) 0 0 1 Reserved Size [15:2] 0 0 |
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