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CS5535-UDC Datasheet(PDF) 90 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 90 Page - National Semiconductor (TI) |
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90 / 555 page  ACC Functional Description (Continued) www.national.com 90 Revision 0.8 Audio Driver Power-up/down Programming Model The ACC contains Machine Specific Registers (MSRs) that relate to a very low level power management scheme, but are discrete from the power management features of the codec and the device driver programming model. This sec- tion covers the power management features for the device driver. See Section 4.3.5 "AC Link Power Management" on page 86 for power management hardware details. The following sections outline how the device driver should perform power management. Power-down Procedure 1) Disable or pause all bus masters using their bus mas- ter command register. 2) It may be necessary to determine if a second codec is being used, and if so, verify that the power-down Semaphore for Secondary Codec bit is set before pro- ceeding (to insure that the modem driver has prepared the second codec for power-down, if necessary). 3) Using the Codec Control register, access the primary codec’s registers and program the codec to power- down. Also, simultaneously write to the AC Link Shut- down bit in the Codec Control register (ACC I/O Offset 0Ch[18]). 4) The ACC and codec will power-down once the com- mand is received by the codec. All of the contents of the ACC and codec registers are preserved during the power-down state. 5) If you wish to enable the GPIO wakeup interrupt, wait for an additional two audio frame periods (42 µs) before setting the GPIO Wakeup Interrupt Enable bit (ACC I/O Offset 00h[29]). Failure to wait will cause false interrupt events to occur. Power-up Procedure 1) If GPIO Wakeup Interrupt Enable (ACC I/O Offset 00h[29]) was set in the power-down procedure, it will automatically be disabled upon power-up. 2) Set the AC Link Warm Reset bit in the Codec Control register (ACC I/O Offset 0Ch[17]). This will initiate the warm reset sequence. 3) Wait for the Codec Ready bit(s) in the Codec Status register (ACC I/O Offset 08h[23:22]) to be asserted before accessing any codec features or enabling any bus masters. Notes: 1) If the GPIO Wakeup Interrupt Enable (ACC I/O Offset 00h[29]) is set, and an interrupt occurs, it is detected and fired, but the interrupt does not wakeup the codec and ACC. The hardware will only wakeup if the soft- ware responds to the interrupt and performs the power-up procedure. 2) Once software has issued a power-down, it must not perform the power-up procedure for at least six audio frame periods (about 0.125 ms or 125 µs). Doing so could lock up the codec or ACC. 3) If the system has cut off power to the codec and restarted it, it is not necessary to initiate a warm reset. The AC Link Shutdown should be cleared manually to restart the operation of the AC Link. |
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