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CS5535-UDC Datasheet(PDF) 85 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 85 Page - National Semiconductor (TI) |
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85 / 555 page  ACC Functional Description (Continued) www.national.com 85 Revision 0.8 Slot 12: GPIO Control This slot allows the ACC to set the value of the AC97 codec’s GPIO output pins. bits [19:4] Value of the GPIO pins (Up to 16 can be implemented) bits [3:0] Reserved 4.3.4.3 AC Link Input Frame (AC_S_IN, AC_S_IN2) The audio input frame data streams correspond to the time division multiplexed bundles of all digital input data coming from the AC97 codec. Each input frame contains 13, 20-bit incoming data slots, except for slot 0; it is 16 bits. Slot 0 is a dedicated slot used for the AC Link protocol. An audio input frame begins with a low-to-high transition of the AC_S_SYNC signal. AC_S_SYNC is synchronous to the rising edge of AC_CLK. The AC97 codec samples the AC_S_SYNC signal on the immediately following falling edge of the bit clock. The AC97 codec transmits data on each following rising edge of AC_CLK. The ACC samples the data on the falling edges of AC_CLK. The serial input stream is MSB justified (MSB first) within each slot, and all non-valid bit positions stuffed with zeroes by the AC97 codec. Slot 0: TAG The first bit of the TAG slot (bit 15) is the Codec_Ready bit. The next 12 bits indicate the validity of the next 12 data slots. Slot 1: Status Address / SLOTREQ Bits The status address is the echo of the register address (index) that was sent to the codec on output slot 1 of the previous output frame. It indicates the address (index) of the register whose data is being returned in slot 2 of the input frame. bit 19 Reserved (Stuffed with 0s) bits [18:12] Control Register Index (Echo of register index for which data is being returned) bits [11:2] SLOTREQ bits (For variable sampling rate) bits [1:0] Reserved (Stuffed with 0s) The SLOTREQ bits support the variable sample rate sig- naling protocol. With normal 48 kHz operation, these bits are always zero. When the AC97 codec is configured for a lower sample rate, some output frames will not contain samples because the AC Link always outputs frames at 48 kHz. The SLOTREQ bits serve as the codec’s instrument to tell the ACC whether it needs a sample for a given slot on the next output frame. For each bit: 0 = Send data; 1 = Do NOT send data. If the codec does not request data for a given slot, the ACC should tag that slot invalid and not send PCM data. The mapping between SLOTREQ bits and out- put slots is given in Table 4-5. The SLOTREQ bits are inde- pendent of the validity of slot 1, and slot 1 will only be tagged valid by the codec if it contains a register index. Slot 2: Status Data The status data slot delivers 16-bit control register read data. bits [19:4] Control Register Read Data (Stuffed with 0s if slot 2 is tagged “invalid” by slot 0) bits [3:0] Reserved (Stuffed with 0s) Slot 3: PCM Record Left Channel Contains the left channel ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slot 4: PCM Record Right Channel Contains the right channel ADC input data (16-bit resolu- tion, MSB first, unused LSBs = 0). Slot 5: Modem Line 1 ADC Contains the modem line 1 ADC input data (16-bit resolu- tion, MSB first, unused LSBs = 0). Slot 6: Optional Microphone Record Data Contains the microphone ADC input data (16-bit resolution, MSB first, unused LSBs = 0). Slots 7-10: Not Used Slots 7-10 are reserved. Slot 11: Modem Headset ADC Contains the modem headset ADC input data (16-bit reso- lution, MSB first, unused LSBs = 0). Table 4-5. SLOTREQ to Output Slot Mapping Bit Slot Request Notes 11 Slot 3 Left Channel Out (BM0) 10 Slot 4 Right Channel Out (BM0) 9 Slot 5 Modem Line 1 Out (BM2) 8 Slot 6 Center Out (BM4 if selected) 7 Slot 7 Left Surround Out (BM6) 6 Slot 8 Right Surround Out (BM6) 5 Slot 9 LFE Out (BM7) 4 Slot 10 Not Supported 3 Slot 11 Handset Out (BM4 if selected) 2 Slot 12 Not Supported |
Similar Part No. - CS5535-UDC |
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Similar Description - CS5535-UDC |
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