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CS5535-UDC Datasheet(PDF) 82 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 82 Page - National Semiconductor (TI) |
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82 / 555 page  ACC Functional Description (Continued) www.national.com 82 Revision 0.8 4.3.1 Audio Bus Masters The ACC includes eight bus mastering units (three for input, five for output). Each bus master corresponds to one or two slots in the AC Link transfer protocol (see Section 4.3.4.1 "AC Link Serial Interface Protocol" on page 83). Table 4-4 lists the details for each bus master. 4.3.2 Bus Master Audio Configuration Registers The bus masters must be programmed by software to con- figure how they transfer data. This is done using their con- figuration registers. These registers determine whether the bus master is active and what parts of memory they have been assigned to transfer. Status registers allow software to read back information on the state of the bus masters. (See Section 5.3.2 "ACC Native Registers" on page 236 for further details on the Bus Master Audio Configuration reg- isters.) 4.3.3 AC Link Overview The AC Link is the interface between the AC97 codec and the ACC. The interface is AC97 v2.1 compliant. Any AC97 codec that supports Sample Rate Conversion (SRC) can be used with the ACC. See Intel Corporation’s “Audio Codec 97” Revision 2.1 component specification for more details. The AC Link protocol defines an input and output frame consisting of 12 “slots” of data. Each slot contains 20 bits, except slot 0, it contains 16 bits. The SYNC signal is gener- ated by the ACC and defines the beginning of an input and an output frame. The serial clock is generated by the AC97 codec. The AC Link is covered in depth in Section 4.3.4.1 "AC Link Serial Interface Protocol" on page 83. It is impor- tant to note that the AC97 codec has its own set of configu- ration registers that are separate from the ACC. These registers are accessible over the serial link. There are reg- isters in the ACC that provide software with an interface to the AC97 codec registers. (See Section 5.3.2 "ACC Native Registers" on page 236 for register descriptions.) Table 4-4. Audio Bus Master Descriptions Bus Master Size Direction AC Link Slot(s) Channel Description BM0 32-bit (16 bits/channel) Output to codec 3 (left) and 4 (right) Left and Right Stereo Main Playback BM1 32-bit (16 bits/channel) Input from codec 3 (left) and 4 (right) Left and Right Stereo Recording BM2 16-bit Output to codec 5 Modem Line 1 DAC Output BM3 16-bit Input from codec 5 Modem Line 1 ADC Input BM4 16-bit Output to codec 6 or 11 (configurable) Center Channel Playback (slot 6) or Headset Playback (slot 11) BM5 16-bit Input from codec 6 or 11 (configurable) Microphone Record (slot 6) or Headset Record (slot 11) BM6 32-bit (16 bits/channel) Output to codec 7 (left) and 8 (right) Left and Right Surround Playback BM7 16-bit Output to codec 9 Low Frequency Effects Playback (LFE) |
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