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CS5535-UDC Datasheet(PDF) 79 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 79 Page - National Semiconductor (TI) |
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79 / 555 page  Revision 0.8 79 www.national.com GLPCI_SB Functional Description (Continued) 4.2.14 CPU Interface Serial (CIS) The CIS provides the system interface between the CS5535 and GX2. The interface supports several modes to send different combinations of 16-bit side-band signals through the CIS signal (ball P3). The sideband signals are synchronized to the PCI clock through 2-stage latching. Whenever at least one of 16 signals is changed, the serial transfer (using the PCI clock) immediately starts to send the information from the South Bridge to the North Bridge. But, if any bit changes within 20 clocks of any previous change, the later change will not be transmitted during the transfer. Another transfer will start immediately after the conclusion of the transfer due to the subsequent change. There are three modes of operation for the CIS signal (ball P3). Note that the transmitted polarity may be different than the “generally defined” polarity state: • Mode A - Non-serialized mode with CIS equivalent to SUSP# (reset mode). Not used in normal operation. • Mode B - Serialized mode with signals SUSP#, NMI, Sleep, and Delayed Sleep. Not used in normal opera- tion. • Mode C - Serialized mode with Mode B signals plus ASMI, and INTR. Used in normal operation. If the GLPCI_MSR_CTRL bit HCD (MSR 51000010h[9]) is set, any in-bound transaction, except in-bound memory writes, will be held for any CIS transfer to complete before claiming completion. Mode selection is programmed in the GLPCI_MSR_CTRL, bits [4:3] (MSR 51000010h). Table 4-3 lists the serial data with corresponding side-band signals. The serial shift register takes the selected side- band signals as inputs. The signal SMI is the ORed result of the SSMI_ASMI_FLAG (SSMI Received Event) bit in GLPCI_SB GLD_MSR_SMI (MSR 51000002h[18]) and the side-band signal ASMI. It also serves as a direct output to the processor. Table 4-3. CIS Serial Bits Assignment and Descriptions Bit Position Mode B Mode C Comment start_0 0 0 Start Bit 0 start_1 0 0 Start Bit 1 data 00 1 1 Reserved data 01 1 1 Reserved data 02 SUSP SUSP Sleep Request data 03 NMI# NMI# Non-Maskable Interrupt data 04 Sleep# Sleep# Power Management Input Disable data 05 Delayed Sleep# Delayed Sleep# Power Management Output Disable data 06 1 ASMI# ASMI or SSMI data 07 1 INTR# Maskable Interrupt out data 08 1 1 Reserved data 09 1 1 Reserved data 10 1 1 Reserved data 11 1 1 Reserved data 12 1 1 Reserved data 13 1 1 Reserved data 14 1 1 Reserved data 15 1 1 Reserved stop_0 1 1 Stop Bit 0 stop_1 1 1 Stop Bit 1 Note: Mode A is not listed since it is a non-serialized mode with CIS equivalent to SUSP# (reset mode). |
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