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CS5535-UDC Datasheet(PDF) 62 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 62 Page - National Semiconductor (TI) |
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62 / 555 page  www.national.com 62 Revision 0.8 Global Concepts and Features (Continued) 3.7.7 Legacy I/O Decoding Table 3-6 details the legacy I/O range for 000h through 4FFh. Each I/O location has a read/write (R/W) capability. Note the following abbreviations: --- Unknown or can not be determined. Yes Read and Write the register at the indicated location. No shadow required. WO Write only. Value written can not be read back. Reads do not contain any useful information. RO Read only. Writes have no effect. Shw The value written to the register can not be read back via the same I/O location. Read back is accomplished via a “Shadow” register located in MSR space. Shw@ Reads of the location return a constant or meaningless value. Shw$ Reads of the location return a status or some other meaningful information. Rec Writes to the location are “recorded” and written to the LPC. Reads to the location return the recorded value. The LPC is not read. Table 3-5. Diverse Device Space Map Except Legacy I/O Device MSR Space (Note 1) I/O Space Memory Space DD Standard GeodeLink Device MSRs plus: SMB LBAR, ACPI LBAR, PM LBAR, GPIO LBAR, MFGPT LBAR, NAND LBAR, KEL LBAR, KEL LBAR, IRQ Mapper LBAR, Legacy Controls, DMA Mappers, Shadow Registers, LPC Controls, and Memory Mask. NOR Flash address control. Located by associated LBAR. Defaults disabled. 008 Bytes SMB, 016 Bytes ACPI, 064 Bytes PM Support, 256 Bytes GPIO and ICFs, 064 Bytes MFGPTs, 016 Bytes NAND Flash, and 032 Bytes IRQ Mapper. All I/O that does not hit one of the items above and does not hit a legacy address, is directed to the LPC bus. 16-Byte KEL Host Controller reg- ister set at LBAR. Defaults dis- abled. NOR Flash per LBAR. All other memory accesses are directed to the LPC bus. Note 1. See Section 3.8 "Standard GeodeLink Device MSRs" on page 67 for register descriptions. Table 3-6. Legacy I/O: 000h-4FFh I/O Addr. Function Size R/W Comment 000h Slave DMA Address - Channel 0 8-bit Yes 16-bit values in two transfers. 001h Slave DMA Counter - Channel 0 8-bit Yes 16-bit values in two transfers. 002h Slave DMA Address - Channel 1 8-bit Yes 16-bit values in two transfers. 003h Slave DMA Counter - Channel 1 8-bit Yes 16-bit values in two transfers. 004h Slave DMA Address - Channel 2 8-bit Yes 16-bit values in two transfers. 005h Slave DMA Counter - Channel 2 8-bit Yes 16-bit values in two transfers. 006h Slave DMA Address - Channel 3 8-bit Yes 16-bit values in two transfers. 007h Slave DMA Counter - Channel 3 8-bit Yes 16-bit values in two transfers. 008h Slave DMA Command/Status - Channels [3:0] 8-bit Shw$ 009h Slave DMA Request - Channels [3:0] 8-bit WO Reads return value B2h. 00Ah Slave DMA Mask - Channels [3:0] 8-bit Shw@ Reads return value B2h. 00Bh Slave DMA Mode - Channels [3:0] 8-bit Shw@ Reads return value B2h. 00Ch Slave DMA Clear Pointer - Channels [3:0] 8-bit WO Reads return value B2h. 00Dh Slave DMA Reset - Channels [3:0] 8-bit WO Reads return value B2h. |
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