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CS5535-UDC Datasheet(PDF) 57 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 57 Page - National Semiconductor (TI) |
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57 / 555 page  Revision 0.8 57 www.national.com Global Concepts and Features (Continued) 3.5 CLOCK CONSIDERATIONS 3.5.1 Clock Domain Definitions Table 3-3 lists the clock sources and domains. Table 3-3. CS5535 Clock Sources and Clock Domains Component Pin Domain Name Description MHZ66_CLK ATAC_LB ATAC Local bus and ATAC core Inverted MHZ66_CLK (Note 1) GLIU_GLA GLIU GLA interface and related logic GLIU_STAT GLIU Statistics Counters GLPCI_GLIU GLPCI_SB GLIU interface and related logic USBC2_GLIU USBC2 GLIU interface and related logic ATAC_GLIU ATAC GLIU interface and related logic DD_GLIU DD GLIU interface and related logic ACC_GLIU ACC GLIU interface and related logic USBC1_GLIU USBC1 GLIU interface and related logic GLCP_GLIU GLCP GLIU interface and related logic MHZ66_CLK divided by two (Note 2) USBC2_LB USBC2 Local bus interface and related logic ACC_LB ACC Local bus interface and related logic USBC1_LB USBC1 Local bus interface and related logic PCI_CLK GLPCI_TRNA GLPCI_SB transaction processing GLPCI_INTF GLPCI_SB interface to PCI bus GLCP_PCI GLCP PCI related logic MHZ48_CLK USBC#2_COR USBC2 core logic USBC#1_COR USBC1 core logic MHZ48_CLK divided by two (Note 2) SMB_COR System Management Bus core logic UART1_COR UART1 core logic UART2_COR UART2 core logic LPC_CLK DD_LB DD Local bus interface and related logic; Includes PIC LPC_COR LPC Controller core logic PIT_COR Programmable Interval Timer core logic DMA_COR 8237 DMA core logic AC_CLK ACC_COR ACC core logic MHZ14_CLK (Note 3) MFGPT_COR_14M MFGPT core logic14 MHz clock PMC_SLP Power Management Controller Sleep logic PIT_REF Programmable Interval Timer reference clock KHZ32_XCI (Note 3) RTC_COR RTC core logic MFGPT_COR_32K MFGPT core logic 32 kHz clock MFGPT_COR_32K_S MFGPT 32kHz clock source; Standby power domain PMC_STB Power Management Controller Standby logic; Standby power domain GPIO_COR GPIO core logic GPIO_COR_S GPIO core logic; Standby power domain TCK (Note 3) TAP_CNTRL JTAG TAP Controller clock source (Note 4) GLCP_DBG GLCP debug logic Note 1. The MHZ66_CLK is first inverted and then fed to all these domains. Note 2. Each domain receives the referenced clock and performs the divide just before the CCU. Note 3. This clock differs from other clocks in this table in that this clock does not utilize a CCU nor is it subject to GLCP control or power management control. Note 4. This logic does not have a fixed clock source. During debug it is switched to the clock domain of interest. It does have a CCU. |
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