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CS5535-UDC Datasheet(PDF) 54 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 54 Page - National Semiconductor (TI) |
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54 / 555 page  www.national.com 54 Revision 0.8 Global Concepts and Features (Continued) Table 3-2. CS5535 MSR Addresses from GX2 Processor Routing Field 0 Routing Field 1 Routing Field 2 Routing Field 3 Routing Field 4 Routing Field 5 GLD Target Name & Address Comment Bits [31:29] Bits [28:26] Bits [25:23] Bits [22:20] Bits [19:17] Bits [16:14] These bits are shifted off to the left and never enter the CS5535. These bits are shifted into posi- tions [31:23] by the time they reach the CS5535. Bits in positions [22:14] are always 0 after shifting. 010 100 010 000 000 000 GLPCI_SB 5100xxxxh This all-zero convention indicates to the GLPCI_SB that the MSR packet coming across the PCI bus is actually for the GLCPI_SB. 010 100 010 000 Non-zero value GLIU 5101xxxxh This non-zero convention indi- cates to the GLPCI_SB that the MSR packet coming across the PCI bus should be forwarded to the GLIU. The GLIU only looks at [22:20] and hence, keeps the packet. 010 100 010 001 Any value Illegal The GLIU can not send any pack- ets back to the port it came from. 010 100 010 010 Any value USBC2 5120xxxxh 010 100 010 011 Any value ATAC 5130xxxxh 010 100 010 100 Any value DD 5140xxxxh 010 100 010 101 Any value ACC 5150xxxxh 010 100 010 110 Any value USBC1 5160xxxxh 010 100 010 111 Any value GLCP 5170xxxxh |
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