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CS5535-UDC Datasheet(PDF) 42 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535-UDC
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535-UDC Datasheet(HTML) 42 Page - National Semiconductor (TI)

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42
Revision 0.8
Signal Definitions (Continued)
2.2.8
GPIOs
Table 2-8 gives the dedicated functions associated with each GPIO. These functions may be invoked by configuring the
associated GPIO to the AUX_IN, AUX_OUT_1, or AUX_OUT_2 modes. (The functions themselves are described in Table
2-9 "GPIOx Available Functions Descriptions" on page 44.) The column “Recommended Use” is a guideline for system
designers to assign GPIO functionality. Any GPIO input can be mapped to an interrupt, ASMI, or PME. Details of configur-
ing the GPIOs are given in Section 5.16 "GPIO Subsystem Register Descriptions" on page 432. All GPIOs have selectable
pull-up or pull-down resistors available on the output, except for those indicated by Note 1 in the “Weak PU/PD” column of
Table 2-8.
Table 2-8. GPIO Options
GPIO
Ball
No.
Power
Domain
Buffer
Type
Post Reset
Recommended
Use
Function Programming Options
Weak
PU/PD
I/O Config
AUX_IN
AUX_OUT_1
AUX_OUT_2
GPIO0
R2
W
PCI
(Note 1)
Note 1.
No internal pull-up/down available. If not used, tie low.
Disabled
PCI_INTA#
(Note 2)
Note 2.
Any GPIO can be used as an interrupt input without restriction. These particular GPIOs have PCI I/O buffer types for complete
PCI bus compatibility. However, such strict compatibility is generally not required.
GPIO1
K3
W
Q7
PU
Disabled
---
AC_BEEP
MFGPT0_C2
GPIO2
B12
W
IDE
(Note 1)
Disabled
---
IDE_IRQ0
GPIO3
E1
W
SMB
(Note 1)
Disabled
DDC_SCL
(Note 3)
UART2 RX
GPIO4
E2
W
SMB
(Note 1)
Disabled
DDC_SDA
(Note 3)
UART2 TX
GPIO5
D3
W
Q7
Auto-
sense
Disabled
---
MFGPT1_RS
MFGPT0_C1
GPIO6
D2
W
Q7
Auto-
sense
Disabled
---
MFGPT0_RS
MFGPT1_C1
MFGPT2_C2
GPIO7
C2
W
PCI
(Note 1)
Disabled
PCI_INTB#
(Note 2)
MFGPT2_C1
SLEEP_X
GPIO8
E3
W
Q7
PU
Disabled
---
UART1_TX
UART1_IR_TX
GPIO9
D1
W
Q7
PU
Disabled
---
UART1_RX or
UART1_IR_RX
GPIO10
C3
W
Q7
PU
Disabled
--- (Note 4)
THRM_ALRM#
GPIO11
A1
W
Q7
PU
Disabled
---
SLP_CLK_EN#
MFGPT1_C2
GPIO12
J3
W
Q7
PD
Disabled
---
AC_S_IN2
SLEEP_Y
GPIO13
F2
W
Q7
PU
Disabled
--- (Note 4)
SLEEP_BUT
GPIO14
G3
W
SMB
(Note 1)
Disabled
--- (Note 5)
SMB_CLK_IN
SMB_CLK_OUT
GPIO15
F1
W
SMB
(Note 1)
Disabled
--- (Note 5)
SMB_DATA_IN
SMB_DATA_OUT
GPIO16
H2
W
PCI
(Note 1) LPC (Note 6)
LPC_AD0
GPIO17
J2
W
PCI
(Note 1)
LPC (Note 6)
LPC_AD1
GPIO18
J1
W
PCI
(Note 1)
LPC (Note 6)
LPC_AD2
GPIO19
K1
W
PCI
(Note 1)
LPC (Note 6)
LPC_AD3
GPIO20
G1
W
PCI
(Note 1)
LPC (Note 6)
LPC_DRQ#
GPIO21
G2
W
PCI
(Note 1)
LPC (Note 6)
LPC_SERIRQ
MFGPT2_RS
GPIO22
H3
W
PCI
(Note 1)
LPC (Note 6)
LPC_FRAME#
GPIO24
C9
S
SMB
(Note 1)
Disabled
---
WORK_AUX
GPIO25
A9
S
Q7
Disabled
---
LOW_BAT#
MFGPT7_C2
GPIO26
B7
S
Q7
Disabled
PME# (Note 7)
MFGPT7_RS
GPIO27
C8
S
Q7
Disabled
---
MFGPT7_C1
32KHZ
GPIO28
A8
S
Q7
Input Enabled
(Note 8)
PWR_BUT#
(Note 9)
PWR_BUT#


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