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CS5535-UDC Datasheet(PDF) 36 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 36 Page - National Semiconductor (TI) |
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36 / 555 page  www.national.com 36 Revision 0.8 Signal Definitions (Continued) IDE_IOR0# B13 O IDE I/O Read. This output is asserted on read accesses to corre- sponding IDE port addresses. When in Ultra DMA/33 mode, this signal is redefined: • IDE_HDMA_RDY - Host DMA Ready for Ultra DMA data-in bursts • IDE_HDMA_DS - Host DMA Data Strobe for Ultra DMA data-out bursts IDE_IOW0# C13 O IDE I/O Write. This output is asserted on write accesses to corre- sponding IDE port addresses. When in Ultra DMA/33 mode, this signal is redefined: • IDE_STOP - Stop Ultra DMA data burst IDE_CS0# B10 O IDE Chip Select 0. This chip select signal is used to select the Com- mand Block registers in IDE Device 0. IDE_CS1# C10 O IDE Chip Select. This chip select signal is used to select the Com- mand Block registers in IDE Device 1. IDE_DREQ0 A14 I DMA Request. The DREQ input is used to request a DMA transfer from the CS5535. The direction of the transfers are determined by the IDE_IOR0# and IDE_IOW0# signals. Note: Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to keep it high during IDE mode. IDE_DACK0# C12 O DMA Acknowledge. The DACK# output acknowledges the IDE_DREQ0 request to initiate DMA transfers. IDE_RDY0 A13 I I/O Ready. When de-asserted, this signal extends the transfer cycle of any host register access when the device is not ready to respond to the data transfer request. When in Ultra DMA/33 mode, this signal is redefined: • IDE_DDMA_DS - Device DMA Data Strobe for Ultra DMA data-in bursts • IDE_DDMA_RDY - Device DMA Ready for Ultra DMA data-out bursts 2.2.3.1 IDE Interface Signals (Continued) Signal Name Ball No. Type Description |
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