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CS5535-UDC Datasheet(PDF) 29 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 29 Page - National Semiconductor (TI) |
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29 / 555 page  Revision 0.8 29 www.national.com Signal Definitions (Continued) 2.1.2 Boot Options Two balls on the device, L2 and L3, the Boot Options Select balls (BOS[1:0]), serve to specify the location of the boot device as the system undergoes a full reset. Since boot devices may reside in Flash or on an IDE device, the IDE/Flash interface is necessarily selected as operating in one of the two modes by the Boot Options. After Reset, the function of these interfaces may be changed with the Ball Options MSR (see Section 2.1.3 "Ball Options"). Both these balls are multiplexed with other functions as identi- fied in Section 2.2.7 "Audio Codec 97 Interface" on page 41 and function as BOS[1:0] only when RESET_OUT# is asserted. Table 2-5 indicates how these two balls should be configured to select the desired boot device. Both balls contain an internal pull-up, active only during reset, so if a ball is required to be high during this time, it may be left unconnected. If a ball is desired to be low during reset, a pull-down (i.e., not a hard tie to ground) should be added. During reset, both balls’ output drivers are in the TRI- STATE mode. 2.1.3 Ball Options Table 2-6 shows the Ball Options MSR (DIVIL MSR 51400015h), through which the function of certain groups of multiplexed balls may be dynamically changed after the reset period ends. Specifically, the functions LPC/GPIO and IDE/Flash groups are selected, and certain individual balls, as specified in the MSR, are controlled. Table 2-5. Boot Options Selection BOS1 (Ball L2) BOS0 (Ball L3) Description 00 Boot from Memory Device on the LPC Bus. IDE pins come up connected to IDE Control- ler (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). 01 Reserved. 10 Boot from NOR Flash on the IDE Bus. IDE pins come up connected to Flash Controller (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). NOR Flash, ROM, or other random access devices must be connected to “FLASH_CS_3”. 11 Boot from Firmware Hub on the LPC Bus. IDE pins come up connected to IDE Control- ler (see Section 2.2.3 "IDE/Flash Interface Signals" on page 35 and Table 2-6 "DIVIL_BALL_OPT" on page 29). Table 2-6. DIVIL_BALL_OPT Bit Name Description 31:12 RSVD Reserved. Reads always return 0. Writes have no effect; by convention, always write 0. 11:10 SEC_BOOT_LOC Secondary Boot Location. Determines which chip select asserts for addresses in the range F00F0000h to F00F3FFFh. Defaults to the same value as boot option: 00: LPC ROM. 01: Reserved . 10: Flash. 11: FirmWare Hub. 9:8 BOOT_OP_ LATCHED(RO) Latched Value of Boot Option (Read Only). For values, see Table 2-5 "Boot Options Selection" on page 29. 7 RSVD Reserved. Reads return value written. By convention, always write 0. Defaults low. |
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