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CS5535-UDC Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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CS5535-UDC Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 555 page  www.national.com 18 Revision 0.8 2.0 Signal Definitions This section defines the signals and describes the external interface of the Geode CS5535. Signal multiplexing has been utilized to a high degree. For example, the IDE and Flash interfaces are multiplexed on the same balls. Config- uration is dependent upon the boot options selected (see Table 2-5 "Boot Options Selection" on page 29). If Flash is selected, the user has the option of using NOR and/or NAND Flash devices. The GPIOs are configurable (e.g., any GPIO input can be mapped to an interrupt, ASMI, or PME). Figure 2-1 shows the signals organized in typical functional groups - not all possible multiplexing is shown. Where signals are multiplexed, the primary signal name is listed first and is separated by a plus sign (+). A slash (/) in a signal name means that the function is always enabled and available (i.e., time multiplexed). Figure 2-1. Typical Signal Groups MHZ66_CLK RESET_WORK# RESET_STAND# MHZ48_CLK KHZ32_XCI KHZ32_XCO MHZ14_CLK System Interface Signals AD[31:0] C/BE[3:0]# PAR FRAME# DEVSEL# IRDY# TRDY# STOP# REQ# GNT# PCI Interface Signals IDE_CS0#+FLASH_CS0#+CE0# IDE_CS1#+FLASH_CS1#+CE1# IDE_IOR0#+FLASH_RE# IDE_IOW0#+FLASH_WE# IDE_AD0+FLASH_AD25/AD[0]+CLE IDE_RDY0+FLASH_IOCHRDY+RDY/BUSY# IDE_DREQ0+FLASH_CS2#+CE2# IDE_DACK0#+FLASH_CS3#+CE3# GPIO2+IDE_IRQ0 IDE/Flash Signals IDE_DATA[7:0]+FLASH_AD[17:10]/IO[7:0] USB_PWR_EN1 USB_PWR_EN2 USB_OC_SENS# USB1_1_DATPOS USB1_1_DATNEG USB1_2_DATPOS USB1_2_DATNEG USB2_1_DATPOS USB2_1_DATNEG USB2_2_DATPOS USB2_2_DATNEG USB Interface GPIO14+SMB_CLK GPIO15+SMB_DATA AC_S_OUT+BOS1 AC_S_IN AC_S_SYNC+BOS0 GPIO1+AC_BEEP LPC Interface IDE_AD[2:1]+FLASH_AD[27:26]/AD[2:1] IDE_DATA[14:8]+FLASH_AD[24:18]/AD[9:3] IDE_DATA15+FLASH_ALE Interface GPIO10+THRM_ALRM# Signals RESET_OUT# WORKING SUSP#/CIS SUSPA# IRQ13 VBAT VSS_BAT1 VSS_BAT2 LVD_EN# PCI_CLK IDE_RESET# AVSS_USB AVDD_USB LPC_CLK LPC_AD[3:0]+GPIO[19:16] LPC_DRQ#+GPIO20 LPC_SERIRQ+GPIO21 LPC_FRAME#+GPIO22 GPIO11+SLP_CLK_EN#+MFGPT_C2 GPIO24+WORK_AUX GPIO25+LOW_BAT#+MFGPT7_C2 GPIO28+PWR_BUT# Signals GPIO0 (PCI_INTA#) GPIO3+UART2_RX (DDC_SCL) GPIO4+UART2_TX (DDC_SDA) GPIO5+MFGPT1_RS+MFGPT0_C1 GPIO6+MFGPT0_RS+MFGPT1_C1+MFGPT2_C2 GPIO7+MFGPT2_C1+SLEEP_X (PCI_INTB#) GPIO8+UART1_TX+UART1_IR_TX GPIO9+UART1_RX+UART1_IR_RX GPIO26+MFGPT7_RS (PME#) GPIO27+MFGPT7_C1+32KHZ GPIOs and “Recommended” Usage TCK TMS TDI TDO T_DEBUG_IN T_DEBUG_OUT LVD_TEST TEST_MODE FUNC_TEST VCORE [Total of 8] VCORE_VSB [Total of 1] VIO [Total of 14] VIO_VSB [Total of 1] VSS [Total of 18] NC [Total of 19] Audio Codec 97 Interface Signals Debug and Interface Signals Manufacturing Power, Ground, and No Connects Note: Bold-italicized signal names in parenthesis denote a “recommended” use for a specific GPIO. See Table 2-8 "GPIO Options" on page 42 for additional details. AC_CLK GPIO12+AC_S_IN2+SLEEP_Y GPIO13+SLEEP_BUT |
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