 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA

HDSP2110S/1S/2S/3S/4S/5S

www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178

10

March 24, 2000-13

Blink Function

Control Word bit, D4, enables or disables the Blink Function.

When D4 is 1, the Blink Function is enabled and all characters

on the display will blink at approximately 2.0 Hz. The Blink

Function will override the Flash Function if both functions are

enabled. When D4 is 0, the Blink Function is disabled. When

using an external clock, the blink rate can be determined by

dividing the clock rate by 28,672. For synchronized blinking on

multiple displays, see the Reset Section.

Self Test

Before starting Self Test, Reset must first be activated. Control

Word bits, D6 and D5, are used for the Self Test Function.

When D6 is 1, the Self Test is initiated. Results of the Self Test

are stored in bits D5. Control Word bit, D5, is a read only bit.

When D5 is 1, Self Test passed is indicated. When D5 is 0, Self

Test failed is indicated. The Self Test function of the IC consists

of two internal routines which exercise major portions of the IC

and illuminates all of the LEDs. The first routine cycles the

ASCII decoder ROM through all states and performs a check

sum on the output. If the check sum agrees with the correct

value, D5 is set to a 1.

Figure 10. UDC Character Map

Figure 11. Flash RAM Access Logic

Figure 12. Control Word Access Logic

Row Data

A2

A1

A0

Row #

Column Data

C1

C2

C3

C4

C5

D4

D3

D2

D1

D0

000

1

5 x 7

Dot Matrix

Pattern

001

2

010

3

011

4

100

5

101

6

110

7

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

0

1

0

X

X

Flash RAM Address for Digits 0–7

D0=Flash Data, 0-Flash Off and 1=Flash On

(Write Cycle)

1

0

1

0

0

X

X

Flash RAM Address for Digits 0–7

D0=Flash Data, 0-Flash Off and 1=Flash On

(Read Cycle)

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

0

1110

Not used for Control Word

Control Word data for a Write Cycle,

see Figure 13

1

0

1

0110

Not used for Control Word

Control Word data for a Read during a

Read Cycle

The second routine provides a visual test of the LEDs using the

drive circuitry. This is accomplished by writing checkered and

inverse checkered patterns to the display. Each pattern is dis-

played for approximately 2.0 seconds. During the self test func-

tion the display must not be accessed. The time needed to

execute the self test function is calculated by multiplying the

clock time by 262,144 (typical time

≈ 4.6 sec.). At the end of the

self test function, the Character RAM is loaded with blanks; the

Control Word Register is set to zeroes except D5, and the

Flash RAM is cleared and the UDC Address Register is set to

all 1.0 s.

Clear Function (see Figures 13 and 14)

Control Word bit, D7 clears the character RAM to 20 hex and

the flash RAM to all zeroes. The RAMs are cleared within three

clock cycles (110

µs minimum, using the internal clock) when

D7 is set to 1. During the clear time the display must not be

accessed. When the clear function is finished, bit 7 of the

Control Word RAM will be reset to a “0”.

Reset Function

The display should be reset on power up of the display

(RST=LOW). When the display is reset, the Character RAM,

Flash RAM, and Control Word Register are cleared.

The display's internal counters are reset. Reset cycle takes

three clock cycles (110

µseconds minimum using the internal

clock). The display must not be accessed during this time.

To synchronize the flashing and blinking of multiple displays, it

is necessary for the display to use a common clock source and

reset all the displays at the same time to start the internal

counters at the same place.

While RST is low, the display must not be accessed by RD

nor WR.