 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA

HDSP2110S/1S/2S/3S/4S/5S

www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178

7

March 24, 2000-13

Figure 7. Block Diagram

÷7

Counter

÷128

Counter

÷3

Counter

OSC

Row

Drivers

Column

Drivers

8 Digit Display

Cursor

Controls

and

Display

MUX

D Latch

Holding

Register

ROM

Word

Decode

ROM

Column

Latch

M

a

s

t

e

r

S

l

a

v

e

Character

RAM

Decode

÷32

Counter

Character

RAM

UDC

Address

Register

Character

Decode

for Display

Character

Decode

(Read/Write)

UDC

RAM

Flash

RAM

Control

Word

Register

Self

Test

Data Bus

25

5

64

16

5

16

4

4

25

Functional Description

The display's user interface is organized into five memory

areas. They are accessed using the Flash Input, FL, and

address lines, A3 and A4. All the listed RAMs and Registers

may be read or written through the data bus. See Table 1. Each

input pin is described in Pin Definitions.

Five Basic Memory Areas

Character RAM

Stores either ASCII (Katakana)

character data or an UDC RAM

address

Flash RAM

1 x 8 RAM which stores Flash data

User-Defined

Character RAM

(UDC RAM)

Stores dot pattern for custom

characters

User-Defined Address

Register (UDC

Address Register)

Provides address to UDC RAM

when user is writing or reading

custom character

Control Word

Register

Enables adjustment of display

brightness, flash individual charac-

ters, blink, self test or clearing

the display

RST can be used to initialize display operation upon power up

or during normal operation. When activated, RST will clear the

Flash RAM and Control Word Register (00H) and reset the

internal counter. All eight display memory locations will be set

to 20H to show blanks in all digits.

FL pin enables access to the Flash RAM. The Flash RAM will

set (D0=1) or reset (D0=0) flashing of the character addressed

by A0–A2.

The 1 x 8 bit Control Word Register is loaded with attribute

data if A3=0.

The Control Word Logic decodes attribute data for proper

implementation.

Character ROM is designed for 128 ASCII characters. The

ROM is Mask Programmable for custom fonts.

The Clock Source could either be the internal oscillator

(CLKSEL=1) of the device or an external clock (CLKSEL=0)

could be an input from another HDSP211X display for the syn-

chronization of blinking for multiple displays.

The Display Multiplexer controls the Row Drivers so no addi-

tional logic is required for a display system.

The Display has eight digits. Each digit has 35 LEDs clustered

into a 5 x 7 dot matrix.