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NM27C512N120 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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NM27C512N120 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 10 page Functional Description (Continued) are held at VIL Address pin A0 is held at VIL for the manu- facturer’s code and held at VIH for the device code The code is read on the eight data pins O0–O7 Proper code access is only guaranteed at 25 C g5 C ERASURE CHARACTERISTICS The erasure characteristics of the device are such that era- sure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms ( ) It should be noted that sunlight and certain types of fluores- cent lamps have wavelengths in the 3000 – 4000 range The recommended erasure procedure for the EPROM is ex- posure to short wave ultraviolet light which has a wave- length of 2537 The integrated dose (ie UV intensity c exposure time) for erasure should be minimum of 15W-seccm2 The EPROM should be placed within 1 inch of the lamp tubes during erasure Some lamps have a filter on their tubes which should be removed before erasure Table III shows the minimum EPROM erasure time for various light intensities An erasure system should be calibrated periodically The distance from lamp to device should be maintained at one inch The erasure time increase as the square of the dis- tance from the lamp (if distance is doubled the erasure time increases by factor of 4) Lamps lose intensity as they age When a lamp is changed the distance has changed or the lamp has aged the system should be checked to make cer- tain full erasure is occurring Incomplete erasure will cause symptoms that can be misleading Programmers compo- nents and even system designs have been erroneously suspected when incomplete erasure was the problem SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices The supply current ICC has three segments that are of interest to the system de- signer the standby current level the active current level and the transient current peaks that are produced by volt- age transitions on input pins The magnitude of these tran- sient current peaks is dependent of the output capacitance loading of the device The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors It is recommended that at least a 01 mF ceramic capacitor be used on every device between VCC and GND This should be a high frequency capacitor of low inherent inductance In addition at least a 47 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices The bulk capacitor should be located near where the power supply is connected to the array The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces Mode Selection The modes of operation of the NM27C512 are listed in Table I A single 5V power supply is required in the read mode All inputs are TTL levels excepts for VPP and A9 for device signature TABLE I Mode Selection Pins CE PGM OE VPP VCC Outputs Mode Read VIL VIL 50V DOUT Output Disable X VIH 50V High Z (Note 1) Standby VIH X 50V High Z Programming VIL 1275V 625V DIN Program Verify VIL VIL 625V DOUT Program Inhibit VIH 1275V 625V High Z Note 1 X can be VIL or VIH TABLE II Manufacturer’s Identification Code Pins A0 A9 07 06 05 04 03 02 01 00 Hex (10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data Manufacturer Code VIL 12V 10001111 8F Device Code VIH 12V 10000101 85 8 |
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