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CS4237B Datasheet(PDF) 45 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 45 Page - Cirrus Logic |
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45 / 114 page  XT = 24.576 MHz CS2 = 0 XT = 16.9344 MHz CS2 = 1 N = DIV5-DIV0 16 ≤ N ≤ 49 for XT = 24.576 MHz 12 ≤ N ≤ 33 for XT = 16.9344 MHz (M set by OSM1,0 in I10) M = 64 for Fs > 24 kHz M = 128 for 12 kHz < Fs ≤ 24 kHz M = 256 for Fs ≤ 12 kHz SRE Alternate Sample Rate Enable. When this bit is set to a one, bits 0-3 of I8 will be ignored, and the sample fre- quency is then determined by CS2, DIV5-DIV0, and the oversampling mode bits OSM1, OSM0 in I10. Note that this register can be overridden (disabled) by IFSE in X11. Extended Register Access (I23) Default = 00000xx0 D7 D6 D5 D4 D3 D2 D1 D0 XA3 XA2 XA1 XA0 XRAE XA4 res ACF ACF ADPCM Capture Freeze. When set, the capture ADPCM accumulator and step size are frozen. This bit must be set to zero for adaptation to continue. This bit is used when pausing a ADPCM capture stream. res Reserved. Must write 0. Could read as 0 or 1. XA4 Extended Register Address bit 4. Along with XA3-XA0, enables ac- cess to extended registers X16, X17, and X25. MODE 3 only. XRAE Extended Register Access Enable. Setting this bit converts this register from the extended address register to the extended data register. To con- vert back to an address register, R0 must be written. MODE 3 only. XA3-XA0 Extended Register Address. Along with XA4, sets the register number (X0-X17+X25) accessed when XRAE is set. MODE 3 only. See the WSS Extended Register section for more details. Alternate Feature Status (I24) Default = x0000000 D7 D6 D5 D4 D3 D2 D1 D0 res TI CI PI CU CO PO PU PU Playback Underrun: When set, indicates the DAC has run out of data and a sample has been missed. PO Playback Overrun: When set, indicates that the host attempted to write data into a full FIFO and the data was discarded. CO Capture Overrun: When set, indicates that the ADC had a sample to load into the FIFO but the FIFO was full. In this case, this bit is set and the new sample is discarded. CU Capture Underrun: Indicates the host has read more data out of the FIFO than it contained. In this condition, the bit is set and the last valid byte is read by the host. PI Playback Interrupt: Indicates an interrupt is pending from the play- back DMA count registers. CI Capture Interrupt: Indicates an interrupt is pending from the capture DMA count registers. TI Timer Interrupt: Indicates an interrupt is pending from the timer registers DS213PP4 CS4237B 45 |
Similar Part No. - CS4237B |
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Similar Description - CS4237B |
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