 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CS4237B Datasheet(PDF) 44 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS4237B Datasheet(HTML) 44 Page - Cirrus Logic |
|
|
44 / 114 page  RLBM Right LINE Bypass Mute. In MODE 3, when set to 1, the analog Right Line Input, RLINE, (bypassing the gain block) to the input mixer is muted. In MODEs 1 & 2, this bit is not avail- able and is internally controlled by RSS1,0 in I1. RLIM Right LINE Input Mute. In MODE 3, when set to 1, the Right Line Input, RLINE, from the volume control to the input mixer is muted. In MODEs 1 & 2, this bit is not avail- able and internally forced on (muted). RLOM Right LINE Output Mute. When set to 1, the Right Line Input, RLINE, from the volume control to the output mixer is muted. When IFM=1 and FMRM=1, FM remapping is en- abled. When WTEN=1 and WTRMD=0, Wavetable remapping is enabled. If either synthesizer remap is enabled, right LINE analog volume is controlled through X1. With remapping the bit definitions are: RR7-RR0 Right Remapped Register. When IFM=1 and FMRM=1, writes to I19 will write the Internal FM regis- ter X7. When WTEN=1 and WTRMD=0, writes to I19 will write the Wavetable synthesis register X17. Timer Lower Base (I20) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 TL7-TL0 Lower Timer Bits: This is the low order byte of the 16-bit timer base register. Writes to this register cause both timer base registers to be loaded into the internal timer; therefore, the upper timer register should be loaded before the lower. Once the count reaches zero, an interrupt is generated, if enabled, and the timer is automatically reloaded with these base registers. Timer Upper Base (I21) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0 TU7-TU0 Upper Timer Bits: This is the high order byte of the 16-bit timer. The time base is determined by the fre- quency base selected from either C2SL in I8 or CS2 in I22. C2SL = 0 - 24.576MHz / 245 (9.969 µs) C2SL = 1 - 16.9344MHz / 168 (9.92 µs) Alternate Sample Frequency Select (I22) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 SRE DIV5DIV4DIV3DIV2 DIV1DIV0 CS2 CS2 Clock 2 Base Select. This bit selects the base clock frequency used for generating the audio sample rate. Note that the part uses only one crystal to generate both clock base frequencies. This bit can be disabled by setting IFSE in X11. 0 - 24.576 MHz base 1 - 16.9344 MHz base DIV5 - DIV0 Clock Divider. These bits select the audio sample frequency for both cap- ture and playback. These bits can be overridden by IFSE in X11. Fs = (2*XT)/(M*N) RLG4-G0 RLINE (Synthesis) RLIM RLOM RLBM To Output Mixer To Input Mixer +12 to -34.5 dB DS213PP4 CS4237B 44 |
Similar Part No. - CS4237B |
|
Similar Description - CS4237B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
