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CS4237B Datasheet(PDF) 42 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 42 Page - Cirrus Logic |
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42 / 114 page  which was written. The Current Count registers cannot be read. When set for MODE 1 or SDC, this register is used for both the Play- back and Capture Base registers. Playback Lower Base (I15) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0 PLB7-PLB0 Lower Base Bits: This register is the lower byte which represents the 8 least significant bits of the 16-bit Playback Base register. Reads from this register return the same value which was written. When set for MODE 1 or SDC, this register is used for both the Playback and Cap- ture Base registers. Alternate Feature Enable I (I16) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 OLB TE CMCE PMCE SF1 SF0 SPE DACZ DACZ DAC Zero: This bit will force the out- put of the playback channel to AC zero when an underrun error occurs 1 - Go to center scale 0 - Hold previous valid sample SPE DSP Serial Port Enable. When set, audio data from the ADCs is sent out SDOUT and audio data from SDIN is sent to the DACs. MCE in R0 must be set to change this bit. 1 - Enable serial port 0 - Disable serial port. ISA Bus used for audio data. SF1,SF0 Serial Format. Selects the format of the serial port when enabled by SPE. MCE in R0 must be set to change these bits. 0 - 64-bit enhanced. Figure 9. 1 - 64-bit. Figure 10. 2 - 32-bit. Figure 11. 3 - ADC/DAC. Figure 12. PMCE Playback Mode Change Enable. When set, it allows modification of the stereo/mono and audio data for- mat bits (D7-D4) for the playback channel, I8. MCE in R0 must be used to change the sample fre- quency. CMCE Capture Mode Change Enable. When set, it allows modification of the stereo/mono and audio data for- mat bits (D7-D4) for the capture channel, I28. MCE in R0 must be used to change the sample fre- quency in I8. TE Timer Enable: This bit, when set, will enable the timer to run and interrupt the host at the specified frequency in the timer registers. OLB Output Level Bit: Provided for back- wards compatibility with the CS4236. This bit does nothing on this chip. Alternate Feature Enable II (I17) Default = 0000x000 D7 D6 D5 D4 D3 D2 D1 D0 TEST TEST TEST TEST APAR res XTALE HPF HPF High Pass Filter: This bit enables a DC-blocking high-pass filter in the digital filter of the ADC. This filter forces the ADC offset to 0. 0 - disabled 1 - enabled XTALE Crystal Enable. Provided for back- wards compatibility with the CS4231A. This bit does nothing on the this part. res Reserved. Must write 0. Could read as 0 or 1. DS213PP4 CS4237B 42 |
Similar Part No. - CS4237B |
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Similar Description - CS4237B |
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