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CS4237B Datasheet(PDF) 41 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 41 Page - Cirrus Logic |
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41 / 114 page  ACI Auto-calibrate In-Progress: This bit indicates the state of calibration. 0 - Calibration not in progress 1 - Calibration is in progress PUR Playback underrun: This bit is set when playback data has not arrived from the host in time to be played. As a result, if DACZ = 0, the last valid sample will be sent to the DACs. This bit is set when an error occurs and will not clear until the Status register (R2) is read. COR Capture overrun: This bit is set when the capture data has not been read by the host before the next sample arrives. The old sample will not be overwritten and the new sample will be ignored. This bit is set when an error condition occurs and will not clear until the Status register (R2) is read. The SER bit in the Status register (R2) is simply a logical OR of the COR and PUR bits. This enables a polling host CPU to detect an error condition while checking other status bits. MODE and ID (I12) Default = 100x1010 D7 D6 D5 D4 D3 D2 D1 D0 1 CMS1 CMS0 res ID3 ID2 ID1 ID0 ID3-ID0 Codec ID: These four bits indicate the ID and initial revisions of the codec. Further revisions are expanded in in- direct register I25 through the CS4236 and C1 for newer chips. These bits are read only. 0001 - Rev B CS4248/CS4231 1010 - All other revisions and parts. See Registers X25 or C1. res Reserved. Must write 0. Could read as 0 or 1. CMS1,0 Codec Mode Select bits: Enables the Extended registers and functions of the part. 00 - MODE 1 01 - Reserved 10 - MODE 2 11 - MODE 3 Monitor Loopback Volume (I13) Default = 000000x0 D7 D6 D5 D4 D3 D2 D1 D0 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 res LBE LBE Loopback Enable: When set to 1, the ADC data is digitally mixed with data sent to the DACs. This bit controls the loopback enable for both chan- nels regardless of how SLBE in X10 is set. 0 - Loopback disabled 1 - Loopback enabled res Reserved. Must write 0. Could read as 0 or 1. LBA5-LBA0 Loopback Attenuation: These bits determine the attenuation of the loop- back from ADC to DAC. The least significant bit represents -1.5 dB, with 000000 = 0 dB. See Table 6. LBA5-LBA0 control left and right channels when SLBE in X10 is clear. When SLBE = 1, these bits only control the left channel and RLBA5- RLBA0 in X10 control the right. Playback Upper Base (I14) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0 PUB7-PUB0 Playback Upper Base: This register is the upper byte which represents the 8 most significant bits of the 16-bit Playback Base register. Reads from this register return the same value DS213PP4 CS4237B 41 |
Similar Part No. - CS4237B |
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Similar Description - CS4237B |
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