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CS4237B Datasheet(PDF) 40 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 40 Page - Cirrus Logic |
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40 / 114 page  Caution: This register, except bits CEN and PEN, can only be written while in Mode Change Enable (either MCE or PMCE). See the Chang- ing Sampling Rate section for more details. Pin Control (I10) Default = 0000000x D7 D6 D5 D4 D3 D2 D1 D0 XCTL1 XCTL0 OSM1 OSM0 DEN DTM IEN res res Reserved. Must write 0. Could read as 0 or 1. IEN Interrupt Enable: This bit enables the interrupt pin. The Interrupt pin will re- flect the value of the INT bit of the Status register (R2). The interrupt pin is active high. 0 - Interrupt disabled 1 - Interrupt enabled DTM DMA Timing Mode. MODE 2 & 3 only. When set, causes the current DMA request signal to be deasserted on the rising edge of the IOW or IOR strobe during the next to last byte of a DMA transfer. When DTM = 0 the DMA request is released on the fall- ing edge of the IOW or IOR during the last byte of a DMA transfer. DEN Dither Enable: When set, triangular pdf dither is added before truncating the ADC 16-bit value to 8-bit, un- signed data. Dither is only active in the 8-bit unsigned data mode. 0 - Dither enabled 1 - Dither disabled OSM1-OSM0 These bits are enabled by setting SRE = 1 in I22. These bits in com- bination with DIV5-DIV0 and CS2 (I22) determine the current sample rate of the WSS Codec when SRE = 1. Note that these bits can be disabled by setting IFSE in X11. 00 - 12kHz < Fs ≤ 24kHz 01 - Fs > 24kHz 10 - Fs ≤ 12kHz 11 - reserved XCTL1-XCTL0 XCTL Control: These bits are reflected on the XCTL1,0 pins of the part. NOTE: These pins are multiplexed with other functions; therefore, they may not be available on a particular design. 0 - TTL logic low on XCTL1,0 pins 1 - TTL logic high on XCTL1,0 pins Error Status and Initialization (I11, Read Only) Default = 00000000 D7 D6 D5 D4 D3 D2 D1 D0 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0 ORL1-ORL0 Overrange Left Detect: These bits determine the overrange on the left ADC channel. These bits are up- dated on a sample by sample basis. 0 - Less than -1.5 dB 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange ORR1-ORR0 Overrange Right Detect: These bits determine the overrange on the Right ADC channel. 0 - Less than -1.5 dB 1 - Between -1.5 dB and 0 dB 2 - Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange DRS DRQ Status: This bit indicates the current status of the DRQs assigned to the WSS Codec. 0 - Capture AND Playback DRQs are presently inactive 1 - Capture OR Playback DRQs are presently active DS213PP4 CS4237B 40 |
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Similar Description - CS4237B |
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