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CS4237B Datasheet(PDF) 29 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 29 Page - Cirrus Logic |
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29 / 114 page  Sound System Codec Register Interface The Windows Sound System codec is mapped via four locations. The I/O base address, WSSbase, is determined by the Plug and Play configuration. The WSSbase supports four direct registers, shown in Table 3. The first two direct registers are used to access 32 indirect registers shown in Table 4. The Index Address register (WSSbase+0) points to the indirect register that is accessed through the Indexed Data register (WSSbase+1). This section describes all the direct and indirect registers for the WSS Codec. Table 5 details a summary of each bit in each register with Ta- bles 6 through 15 illustrating the majority of decoding needed when programming the WSS logical device, and are included for reference. When enabled, the WSS Codec default state is defined as MODE 1. MODE 1 is backwards compatible with the CS4248 and only allows ac- cess to the first 16 indirect registers. Putting the part in MODE 2 or MODE 3, using CMS1,0 bits in the MODE and ID register (I12), allows ac- cess to indirect registers 16 through 31. Putting the part in MODE 3 also allows access to the extended registers through I23 and other ex- tended features in the indirect registers. DIRECT MAPPED REGISTERS The first two WSS Codec registers provide indi- rect accessing to more codec registers via an index register. The other two registers provide status information and allow audio data to be transferred to and from the WSS Codec without using DMA cycles or indexing. Note that register defaults are listed in binary form with reserved bits marked with ’x’ to indi- cate unknown. To maintain compatibility with future parts, these reserved bits must be written as 0, and must be masked off when the register is read. The current value read for reserved bits is not guaranteed on future revisions. Direct Registers: (R0-R3) Address Reg. Register Name WSSbase+0 R0 Index Address register WSSbase+1 R1 Indexed Data register WSSbase+2 R2 Status register WSSbase+3 R3 PIO Data register Table 3. WSS Codec Direct Register Index Register Name I0 Left ADC Input Control I1 Right ADC Input Control I2 Left Aux #1 Volume I3 Right Aux #1Volume I4 Left Aux #2 Volume I5 Right Aux #2 Volume I6 Left DAC (PC Wave) Volume I7 Right DAC (PC Wave) Volume I8 Fs & Playback Data Format I9 Interface Configuration I10 Pin Control I11 Error Status and Initialization I12 MODE and ID I13 Monitor Loopback Volume I14 Playback Upper Base Count I15 Playback Lower Base Count I16 Alternate Feature Enable I I17 Alternate Feature Enable II I18 Left Line (Synthesizer) Volume I19 Right Line (Synthesizer) Volume I20 Timer Low Byte I21 Timer High Byte I22 Alternate Sample Frequency I23 Extended Register Access (X regs) I24 Alternate Feature Status I25 Compatibility ID I26 Mono Input & Output Control I27 Reserved I28 Capture Data Format I29 Reserved I30 Capture Upper Base Count I31 Capture Lower Base Count Table 4. WSS Codec Indirect Registers DS213PP4 CS4237B 29 |
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