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CS4237B Datasheet(PDF) 28 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 28 Page - Cirrus Logic |
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28 / 114 page  pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sam- ple. Note that different audio data types will require a different number of 8-bit transfers. DMA Interface The second type of parallel bus cycle from the WSS Codec is a DMA transfer. DMA cycles are distinguished from PIO register cycles by the as- se rt ion of a DR Q fol lowe d b y a n acknowledgment by the host by the assertion of DACK (with AEN high). While the acknow- ledgment is received from the host, the WSS Codec assumes that any cycles occurring are DMA cycles and ignores the addresses on the address lines. The WSS Codec may assert the DMA request signal at any time. Once asserted, the DMA re- quest will remain asserted until a complete DMA cycle occurs to the part. DMA transfers may be terminated by resetting the PEN and/or CEN bits in the Interface Configuration register (I9), de- pending on the DMA that is in progress (playback, capture, or both). Termination of DMA transfers may only happen between sample transfers on the bus. If DRQ goes active while resetting PEN and/or CEN, the request must be acknowledged with DACK and a final sample transfer completed. DMA CHANNEL MAPPING Mapping of the WSS Codec’s DRQ and DACK onto the ISA bus is accomplished by the Plug and Play configuration registers. If the Plug and Play resource data specifies only one DMA channel for the Codec (or the codec is placed in SDC mode) then both the playback and capture DMA requests should be routed to the same DRQ/DACK pair (DMA Channel Select 0). If the Plug and Play resource data specifies two DMA channels for the Codec, then the playback DMA request will be routed to the DMA pair specified by the DMA Channel Select 0 resource data, and the capture DMA requests will be routed to the DMA pair specified by the DMA Channel Select 1 resource data. DUAL DMA CHANNEL MODE The WSS Codec supports a single and a dual DMA channel mode. In dual DMA channel mode, playback and capture DMA requests and acknowledges occur on independent DMA chan- nels. In dual DMA mode, SDC should be set to 0. The Playback- and Capture-Enables (PEN, CEN, I9) can be changed without a Mode Change Enable (MCE, R0). This allows for proper full duplex control where applications are independently using playback and capture. SINGLE DMA CHANNEL (SDC) MODE When two DMA channels are not available, the SDC mode forces all DMA transfers (capture or playback) to occur on a single DMA channel (playback channel). The trade-off is that the WSS Codec will no longer be able to perform simultaneous DMA capture and playback. To enable the SDC mode, set the SDC bit in the Interface Configuration register (I9). With the SDC bit asserted, the internal workings of the WSS Codec remain exactly the same as dual mode, except for the manner in which DMA re- quest and acknowledges are handled. The playback of audio data will occur on the playback channel exactly as dual channel opera- tion; however, the capture audio channel is now diverted to the playback channel. Alternatively stated, the capture DMA request occurs on DMA channel select 0 for the WSS Codec. (In MODEs 2 and 3, the capture data format is al- ways set in register I28.) If both playback and capture are enabled, the default will be playback. SDC does not have any affect when using PIO accesses. DS213PP4 CS4237B 28 |
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