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CS4237B Datasheet(PDF) 27 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 27 Page - Cirrus Logic |
27 / 114 page MODE 1. Except for the Capture Data Format (I28), Capture Base Count (I30/31), and Alter- nate Feature Status (I24) registers, all other Mode 2 functions retain their values when re- t ur ni n g to M od e 1 . T h e WS S C ode c is ba ckwa rds co mp ati ble wit h t he CS4236, CS4232, CS4231 and CS4248. The additional MODE 2 functions are: full-du- plex support, a programmable timer, Mono In and Mono Out support. MODE 3 is selected by setting CMS1,0 to 11. MODE 3 allows access to new bits in the indi- rect registers I0-I31, and allows access to a third set of "extended registers" which are designated X0-X17+X25. The extended registers are ac- cessed through I23. The additional MODE 3 functions are: 1. A full symmetrical mixer. This changes the in- put multiplexer to a input mixer. 2. Independent sample frequency control on the ADCs and DACs. 3. Programmable Gain and Attenuation on the Microphone inputs. 4. Independent control over the volume of inter- nal FM synthesis and external wavetable. 5. Volume control on the DSP serial port input data. 6. Stereo volume on the monitor feedback path. FIFOs The WSS Codec contains 16-sample FIFOs in both the playback and capture digital audio data paths. The FIFOs are transparent and have no programming associated with them. When playback is enabled, the playback FIFO continually requests data until the FIFO is full, and then makes requests as positions inside the FIFO are emptied, thereby keeping the playback FIFO as full as possible. Thus when the system cannot respond within a sample period, the FIFO starts to empty, avoiding a momentary loss of audio data. If the FIFO runs out of data, the last valid sample can be continuously output to the DACs (if DACZ in I16 is set) which will elimi- nate pops from occurring. When capture is enabled, the capture FIFO tries to continually stay empty by making requests every sample period. Thus when the system can- not respond within a sample period, the capture FIFO starts filling, thereby avoiding a loss of data in the audio data stream. WSS Codec PIO Register Interface Four I/O mapped locations are available for ac- cessing the Codec functions and mixer. The control registers allow access to status, audio data, and all indirect registers via the index reg- isters. The IOR and IOW signals are used to define the read and write cycles respectively. A PIO access to the Codec begins when the host puts an address on to the ISA bus which matches WSSbase and drives AEN low. WSSbase is pro- grammed during a Plug and Play configuration sequence. Once a valid base address has been decoded then the assertion of IOR will cause the WSS Codec to drive data on the ISA data bus lines. Write cycles require the host to assert data on the ISA data bus lines and strobe the IOW signal. The WSS Codec will latch data into the PIO register on the rising edge of the IOW strobe. The audio data interface typically uses DMA re- quest/grant pins to transfer the digital audio data between the WSS Codec and the bus. The WSS Codec is responsible for asserting a request sig- nal whenever the Codec’s internal buffers need updating. The bus responds with an acknowledge signal and strobes data to and from the Codec, 8 bits at a time. The WSS Codec keeps the request DS213PP4 CS4237B 27 |
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