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CS4237B Datasheet(PDF) 14 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 14 Page - Cirrus Logic |
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14 / 114 page  I/O ADDRESS DECODING The logical devices use 10-bit or 12-bit address decoding. The Synthesizer, Sound Blaster, Game Port, MPU-401, CDROM, and Modem devices support 10-bit address decoding, while the Win- dows Sound System and Control devices support 12-bit address decoding. Devices that support 10-bit address decoding, require A10 and A11 be zero for proper decode; therefore, no aliasing oc- curs through the 12-bit address space. To prevent aliasing into the upper address space, a "16-bit decode" option may be used, where the upper address bits SA12 through SA15 are con- nected to the part. SA12-SA15 are then decoded to be 0,0,0,0 for all logical device address de- coding. When the upper address bits are used, the CDROM and Modem interfaces are no longer available since the upper address pins are multiplexed with the CDROM and Modem inter- faces (See Reset and Power Down section). If the CDROM or Modem is needed, the circuit shown in Figure 2 can replace the SA12 through SA15 pins and provide the same functionality. Four cascaded OR gates, using a 74ALS32, can replace the ALS138 in Figure 2, but causes a greater delay in address decoding. DMA CYCLES The part supports up to three 8-bit ISA-compat- ible DMA channels. The default hardware connections, which can be changed through the hardware configuration data, are: DMA A = ISA DMA channel 0 DMA B = ISA DMA channel 1 DMA C = ISA DMA channel 3 The typical configuration would require two DMA channels. One for the WSS Codec and Sound Blaster playback, and the other for WSS Codec capture (to support full-duplex). The CDROM, if used, can also support a DMA chan- nel, although this is not typical. DMA cycles are distinguished from control reg- ister cycles by the generation of a DRQ (DMA Request). The host acknowledges the request by generating a DACK (DMA Acknowledge) sig- nal. The transfer of audio data occurs during the DACK cycle. During the DACK cycle the ad- dress lines are ignored. The digital audio data interface uses DMA re- quest/grant pins to transfer the digital audio data between the part and the ISA bus. Upon receipt of a DMA request, the host processor responds with an acknowledge signal and a command strobe which transfers data to and from the part, eight bits at a time. The request pin stays active until the appropriate number of 8-bit cycles have occurred. The number of 8-bit transfers will vary depending on the digital audio data format, bit resolution, and operation mode. The DMA request signal can be asserted at any time. Once asserted, the DMA request will re- main asserted until a complete DMA cycle occurs. A complete DMA cycle consists of one or more bytes depending on which device inter- nal to the part is generating the request. SA12 SA13 SA14 SA15 AEN +5V 1 4 C B A 3 2 15 G1 6 G2B G2A 5 Y0 Y6 Y5 Y4 Y3 Y2 Y1 Y7 74ALS138 AEN ISA Bus Figure 2. 16-bit Decode Circuit DS213PP4 CS4237B 14 |
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