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CS4237B Datasheet(PDF) 89 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 89 Page - Cirrus Logic |
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89 / 114 page  range that is four bytes. If the address range is specified to be eight bytes, then XA2 becomes an output for SA2 from the ISA bus. Pin XCTL1/SINT/ACDCS/DOWN is initially controlled by the VCEN bit in the Hardware Configuration data. If VCEN is zero, this pin be- comes an output for XCTL1 when the state of the XIOW pin is sampled high during a high to low transition of the RESDRV pin. This pin also becomes an output for ACDCS if ACDbase is programmed to a non-zero value. If XIOW is sampled low and ACDbase is never programmed to a non-zero value, SINT becomes an input for the external Synthesizer interrupt. XIOW has an internal pullup resistor. ACDCS takes prece- dence over the other two functions. The first time ACDbase is programmed to a non-zero value, the pin converts to ACDCS. The only way to convert back to XTAL1 or SINT is to reset the part. VCEN has the highest precedence and will cause this pin to convert to the DOWN function whenever VCEN is set. Reset and Power Down A RESDRV pin places the part into maximum power conservation mode. When RESDRV goes high, the PnP registers are reset - all logical de- vices are disabled, all analog outputs are muted, and the voltage reference then slowly decays to ground. When RESDRV is brought low, an in- itialization procedure begins which causes a full calibration cycle to occur. When initialization is completed, the registers will contain their reset value and the part will be isolated from the bus. RESDRV is required whenever the part is pow- ered up. The initialization time varies based on whether an E 2PROM is present or not and the size of the data in the E 2PROM. After RESDRV goes low, the CS4236 should not be written to for approximately one and one half second to guarantee that the part is ready to respond to commands. The exact timing is specified in the Timing Section in the front of this data sheet. Software low-power states are available through bits in the Control logical device register space. This part supports the same power down bits contained in the CS4232; however, new power down modes are provided in CTRLbase+2 that allow for a more efficient power management routine. This register allows individual blocks within the part to be powered down. See the CONTROL INTERFACE section for more infor- mation. Multiplexed Pin Configuration On the high to low transition of the RESDRV pin, the part samples the state of the XIOR and XIOW pins. Both of these pins have internal 100k Ω pullups to +5V. If either of these pins is pulled low externally, they must be buffered be- fore connecting to a TTL input (as in a CDROM port) since TTL cannot be pulled low. The state of XIOR at the time RESDRV is brought low determines the function of the CDROM interface pins. If XIOR is sampled high, then CDCS, CDACK, CDINT, CDRQ are used to input SA12, SA13, SA14, SA15 respec- tively. If XIOR is sampled low (external pulldown) then CDCS, CDACK, CDINT, CDRQ become the standard CDROM interface pins. Since many CDROM drives do not use DMA, the CDRQ and CDACK pins are further multi- plexed with MCS and MINT respectively. MCS is the Modem chip select that responds to COM- base addresses, and MINT is the modem interrupt input. These two pins comprise logical device 5. The first time COMbase is pro- grammed to non-zero (assuming XIOR wa s sampled low), CDACK/MCS and CDRQ/MINT switch to MCS and MINT respectively. Once this switch occurs, the only way to revert to the CDROM DMA pins is to reset the part or re- move power. The XCTL1/SINT/ACDCS/DOWN pin state is first determined by VCEN. If VCEN is set this pin is forced to the DOWN volume control pin. DS213PP4 CS4237B 89 |
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Similar Description - CS4237B |
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