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CS4237B Datasheet(PDF) 87 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 87 Page - Cirrus Logic |
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87 / 114 page  The Interrupt Enable (IEN) bit in the Pin Control register (I10) determines whether the interrupt assigned to the WSS Codec responds to the in- terrupt event. When the IEN bit is low, the interrupt is masked and the IRQ pin assigned to the WSS Codec is held low. However, the INT bit in the Status register (R2) always responds to the counter. Error Conditions Data overrun or underrun could occur if data is not supplied to or read from the WSS Codec in an appropriate amount of time. The amount of time for such data transfers depends on the fre- quency selected within the WSS Codec. Should an overrun condition occur during data capture, the last whole sample (before the over- run condition) will be read by the DMA interface. A sample will not be overwritten while the DMA interface is in the process of transfer- ring the sample. Should an underrun condition occur in a play- back case the last valid sample will be output (assuming DACZ = 0) to the digital mixer. This will mask short duration error conditions. When the next complete sample arrives from the host computer the data stream will resume on the next sample clock. The overrun and underrun error bits in the Alter- nate Feature Status register, I24, are cleared by first clearing the condition that caused the over- run or underrun error, followed by writing the particular bit to a zero. As an example, to clear the playback underrun bit PU, first a sample must be sent to the WSS Codec, and then the PU bit must be written to a zero. DIGITAL HARDWARE DESCRIPTION The best example of hardware connection for the different sections of this part such as joystick connector, ISA bus, and peripheral port connec- tions is the Reference Design Data Sheet. The Reference Design Data Sheet contains all the schematics, layout plots and a Bill of Materials; thereby providing a complete example. Bus Interface The ISA bus interface is capable of driving a 24mA data bus load and therefore does not re- quire any external data bus buffering. See the Reference Design Data Sheet for a typical con- nection diagram. Volume Control Interface Three hardware master volume control pins are supported: volume up, volume down, and mute. Hardware volume control is enabled by setting the VCEN bit in the Hardware Configuration data, byte 7 (Misc. Config. Byte). Once VCEN is set, the SCS/UP pin converts to the volume up function and the XTAL1/SINT/ACDCS/DOWN pin converts to the volume down function. The volume control pins affect the master volume control output after the analog output mixer. The UP and DOWN pins, when low, increment and decrement the master volume. These two pins would use SPST momentary switches. The MUTE pin supports three options: push-on/push- off, mome ntary (similar to th e up/d own functions), and non-existent where pressing up and down simultaneously mutes the output vol- ume. As shown in Figure 24, the three pins require external pullups and are active low. The circuit also contains an optional RC for EMI and ESD protection. The volume control range is +12 to -36 dB in 2 dB steps. Pressing the up button, increments the volume. Pressing the down button, decre- ments the volume. Holding either of these buttons in the low state causes the volume to to continue changing. The mute function is supported using three for- mats. These formats are selected using the VCF1 and VCF0 bits in the Hardware Configuration data, Global Config. byte. DS213PP4 CS4237B 87 |
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