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CS4237B Datasheet(PDF) 86 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 86 Page - Cirrus Logic |
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86 / 114 page  CAPTURE DMA REGISTERS The Capture DMA Base registers (I30/31) pro- vide a second pair of Base registers that allow full-duplex DMA operation. With full-duplex op- eration captur e and playback can occur simultaneously. These registers are provided in MODE 2 and 3 only. When the capture Current Count register rolls under, the Capture Interrupt bit, CI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Capture In- terrupt bit, CI (I24). Digital Loopback Digital Loopback is enabled via the LBE bit in the Loopback Control register (I13). This loop- back routes the digital data from the ADCs to the DACs. There are two Methods of control- ling this loopback. The first method does not allow separate control over the attenuation level of the left and right channels. Changes to the attenuation bits of register I13 will simultane- ously affect both the left and the right channels. The other method of controlling loopback, is to set the SLBE bit in register X10. This separates the attenuation levels of the left and right chan- nels. With SLBE enabled, the attenuation bits of register I13 only control the left channel, and the attenuation bits of register X10 control the right channel. The LBE bit in register I13 still en- ables, or disables digital loopback for both channels. Loopback is then summed into the digital mixer. The digital loopback is illustrated in Figure 4. Since the WSS Codec allows selec- tion of different data formats between capture and playback, if the capture channel is set to mono and the playback channel set to stereo, the mono input (mic) data will be mixed into both channels of the output mixer. If the sum of the digital mixer inputs is greater than full scale, WSS Codec will send the appro- priate full scale value to the DACs (clipping). Timer Registers The Timer registers are provided for synchroni- zation, watch dog and other functions where a high resolution time reference is required. This counter is 16 bits and the exact time base, listed in the register description, is determined by the clock base frequency selected. The Timer register is set by loading the high and low registers to the appropriate values and set- ting the Timer Enable bit, TE, in the Alternate Feature Enable register (I16). This value will be loaded into an internal Current Count register and will decrement at approximately a 10 µsec rate. When the value of the Current Count regis- ter reaches zero, an interrupt will be posted to the host and the Timer Interrupt bit, TI, is set in the Alternate Feature Status register (I24). On the next timer clock the value of the Timer regis- ters will be loaded into the internal Current Count register and the process will begin again. The interrupt is cleared by any write to the Status register (R2) or by writing a "0" to the Timer Interrupt bit, TI, in the Alternate Feature Status register (I24). WSS Codec Interrupt The INT bit of the Status register (R2) always reflects the status of the WSS Codec’s internal interrupt state. A roll-over from any Current Count register (DMA playback, DMA capture, or Timer) sets the INT bit. This bit remains set until cleared by a write of ANY value to Status regis- ter (R2), or by clearing the appropriate bit or bits (PI, CI, TI) in the Alternate Feature Status regis- ter (I24). DS213PP4 CS4237B 86 |
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