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CS4237B Datasheet(PDF) 85 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 85 Page - Cirrus Logic |
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85 / 114 page  reading until the FIFO is empty, at which time the requests will stop. When ACF is cleared, the ADPCM adaptation will continue. When PEN is cleared (playback disabled), the ADPCM block’s accumulator and step size are cleared. When PEN is set, the ADPCM block will start converting. When pausing the playback stream is desired, audio data should not be sent to the codec which will cause a data underrun. This can be accomplished by disabling the DMA controller or not sending data in PIO mode. The underrun will be detected by the WSS Codec and the adaptation will freeze. When data is sent to the codec, adaptation will resume. It is critical that all playback ADPCM samples are sent to the codec, since dropped samples will cause errors in adaptation. Whereas toggling PEN resets the accumulator and step size, the APAR bit (I17) only resets the accumulator without affecting the step size. DMA Registers The DMA registers allow easy integration of this part into ISA systems. Peculiarities of the ISA DMA controller require an external count mechanism to notify the host CPU of a full DMA buffer via interrupt. The programmable DMA Base registers provide this service. The act of writing a value to the Upper Base register causes both Base registers to load the Current Count register. DMA transfers are en- abled by setting the PEN/CEN bit while PPIO/CPIO is clear. (PPIO/CPIO can only be changed while the MCE bit is set.) Once trans- fers are enabled, each sample that is transferred by a DMA cycle will decrement the Current Count register (with the exception of the ADPCM format) until zero is reached. The next sample after zero generates an interrupt and re- loads the Current Count registers with the values in the Base registers. For all data formats except ADPCM, the DMA Base registers must be loaded with the number of samples, minus one, to be transferred between "DMA Interrupts". Stereo data contains twice as many samples as mono data; however, 8-bit data and 16-bit data contain the same number of sam- ples. Symbolically: DMA Base register16 = NS - 1 Where NS is the number of samples transferred between interrupts and the "DMA Base regis- ter16" consists of the concatenation of the upper and lower DMA Base registers. For the ADPCM data format, the contents of the DMA Base registers is calculated differently from any other data format. The Base registers must be loaded with the number of BYTES to be transferred between "DMA interrupts", divided by four, minus one. The same equation is used whether the data format is stereo or mono ADPCM. Symbolically: DMA Base register16 = Nb/4 - 1 Where Nb is the number of BYTES transferred between interrupts and the "DMA Base regis- ter16" consists of the concatenation of the upper and lower DMA Base registers. PLAYBACK DMA REGISTERS The playback DMA registers (I14/15) are used for sending playback data to the DACs in MODE 2 and 3. In MODE 1, these registers (I14/15) are used for both playback and capture; therefore, full-duplex DMA operation is not pos- sible. When the playback Current Count register rolls under, the Playback Interrupt bit, PI, (I24) is set causing the INT bit (R2) to be set. The interrupt is cleared by a write of any value to the Status register (R2), or writing a "0" to the Playback Interrupt bit, PI (I24). DS213PP4 CS4237B 85 |
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