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CS4237B Datasheet(PDF) 80 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 80 Page - Cirrus Logic |
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80 / 114 page  CONVERTER CALIBRATION (CAL1,0 = 01) This calibration mode calibrates the ADCs and the DACs, but does not calibrate any of the ana- log mixing channels. This is the second longest calibration mode, taking 321 sample periods at 44.1 kHz. Because the analog mixer is not cali- brated in this mode, any signals fed through the mixer will be unaffected. The calibration se- quence is as follows: The DACs are muted The ADCs are calibrated The DACs are calibrated The DACs are unmuted DAC CALIBRATION (CAL1,0 = 10) This calibration mode only clears the DACs (playback) interpolation filters leaving the ADC unaffected. This is the second fastest calibration mode (no cal. is the fastest) taking 120 sample periods at 44.1 kHz to complete. The calibration sequence is as follows: The DACs are muted The DAC filters are cleared The DACs are unmuted FULL CALIBRATION (CAL1, 0 = 11) This calibration mode calibrates all offsets, ADCs, DACs, and analog mixers. Full calibra- tion will automatically be initiated on power up or anytime the WSS Codec exits from a full power down state. This is the longest calibration mode and takes 450 sample periods at 44.1 kHz to complete. The calibration sequence is as fol- lows: All outputs are muted (DACs and mixer) The mixer is calibrated The ADCs are calibrated The DACs are calibrated All outputs are unmuted Changing Sampling Rate The internal states of the WSS Codec are syn- chronized by the selected sampling frequency. The sample frequency can be set in one of three fashions. The standard WSS Codec method uses the Fs & Playback Data Format register (I8) to set the sample frequency. The changing of either the clock source or the clock frequency divide requires a special sequence for proper WSS Codec operation: 1) Place the WSS Codec in Mode Change En- able using the MCE bit of the Index Address register (R0). 2) During a single write cycle, change the Clock Frequency Divide Select (CFS) and/or Clock 2 Base Select (C2SL) bits of the Fs & Playback Data Format register (I8) to the de- sired value. (The data format may also be changed.) 3) The WSS Codec resynchronizes its internal states to the new frequency. During this time the WSS Codec will be unable to respond. Writes to the WSS Codec will not be recog- nized and reads will always return the value 80 hex. 4) The host now polls the WSS Codec’s Index Address register (R0) until the value 80 hex is no longer returned. On slow processor sys- tems, 80h may occur to fast; therefore, it may never be seen by software. 5) Once the WSS Codec is no longer responding to reads with a value of 80 hex, normal op- eration can resume and the WSS Codec can be removed from MCE. A second method of changing the sample fre- quency is to disable the sample frequency bits in I8 (lower four bits) by setting SRE in I22. When this bit is set, OSM1 and OSM0 in I10, along DS213PP4 CS4237B 80 |
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Similar Description - CS4237B |
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