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CS4237B Datasheet(PDF) 76 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 76 Page - Cirrus Logic |
76 / 114 page ![]() Modem Interface The modem interface, Logical Device 5 (LD5) consist of: MCS - Modem Chip Select MINT - Modem Interrupt The other signals such as address bits, data strobes, data, and reset are provided by the Ex- ternal Peripheral Port. The interface allows the host computer to access up to eight I/O mapped locations. The Modem signals are multiplexed with both the upper ISA address pins, and the CDROM DMA pins. To enable the Modem, first a pull- down resistor must be placed on XIOR which disables the upper ISA address pins. Second, the Modem base address, COMbase, must be pro- grammed to a non-zero value which will convert the SA13/CDACK/MCS pin to the modem chip select MCS, and the SA15/CDRQ/MINT pin to the modem interrupt pin MINT. Once these two pins switch to modem pins, they can only be changed by resetting the part. COMbase, Logical Device 5 base address 0, is programmed via PnP or the SLAM method. The polarity of MINT is programmable via Hardware Configuration data, IHM in byte 7, or through CTRLbase+1. The default is active low (IHM = 0). DSP SERIAL AUDIO DATA PORT The WSS Codec includes a DSP serial audio in- terface for transferring digital audio data between the part and an external serial device such as a DSP processor. The DSP serial port pins are multiplexed with either the #2 joystick inputs of the Game Port interface or a portion of the XD peripheral bus. The selection is made via the SPS bit located in Control register C8, or the Global Config. byte in the Hardware Configura- tion data. If SPS is 0, the joystick B pins convert to the DSP serial port when SPE is set (MCE must be 1 to change SPE). If SPS is 1, XD<4:1> convert to the DSP serial port when SPE is set. In this case, SD<7:0> is disabled on reads of pe- ripheral port addresses (CDROM, modem, etc.) since XD<7:0> is no longer available. The DSP audio serial port is software enabled via the SPE bit in the WSS Codec indirect regis- ter I16. The ISA interface is fully active in this mode. While the serial port is enabled, audio data may still be read from the ADCs over the ISA bus, and the DACs will sum data from the SDIN pin, the parallel ISA bus data, and the in- ternal FM synthesizer engine. The serial port sample frequency is always 44.1 kHz regardless of the ISA bus sample frequency, and the data format is always two’s complement 16-bit linear. FSYNC and SCLK are always output from the part when the serial port is enabled. The serial port can be configured in one of four serial port formats, shown in Figures 9-12. SF1 and SF0 in I16 select the particular format. MCE in R0 must be set to change SF1/0. Both left and right audio words are always 16 bit two’s complement. When the mono audio format is selected, the right channel output is set to zero and the left channel input is summed to both DAC channels. The first format - SPF0, shown in Figure 9, is called 64-bit enhanced. This format has 64 SCLKs per frame with a one bit period wide FSYNC that precedes the frame. The first 16 bits occupy the left word and the second 16 bits oc- cupy the right word. The last 32 bits contain four status bits and 28 zeros. This is the only mode that contains status information. The second serial format - SPF1, shown in Fig- ure 10, is called 64-bit mode. This format has 64 SCLKs per frame, with FSYNC high transitions at the start of the left data word and low transi- tions at the start of the right data word. Both the left and right data words are followed by 16 ze- ros. DS213PP4 CS4237B 76 |
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