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CS4237B Datasheet(PDF) 72 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 72 Page - Cirrus Logic |
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72 / 114 page  MPU-401 INTERFACE The MPU-401 is an intelligent MIDI interface that was introduced by Roland in 1984. Voyetra Technologies subsequently introduced an IBM- PC plug in card that incorporated the MPU-401 functionality. The MPU-401 has become the de- facto standard for controlling MIDI devices via IBM-PC compatible personal computers. Although the MPU-401 does have some intelli- gence, a non-intelligent mode is available in which the MPU-401 operates as a basic UART. By incorporating hardware to emulate the MPU- 4 01 in UART mo de, MIDI ca pab ili ty is supported. MPU-401 Register Interface The MPU401 logical device software interface occupies 2 I/O locations, utilizes 10-bit address de cod ing , and is l oca ted at PnP address ’MPUbase’. 10-bit addressing requires that the upper address bits be 0 to decode a valid ad- dress, i.e. no aliasing occurs. The standard base address is 330h. This device also uses an inter- rupt, typically 9. The PnP alignment for the MPU-401 must be a multiple of 8. MPUbase+0 is the MIDI Transmit/Receive port and MPUbase+1 is the Command/Status port. In addition to I/O decodes the only additional func- tionality required from an ISA bus viewpoint is the generation of a hardware interrupt whenever data has been received into the receive buffer. MIDI Transmit/Receive Port, MPUbase+0, default = xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 TR7-TR0 The MIDI Transmit/Receive Port is used to send and receive MIDI data as well as status information that was returned from a previously sent command. All MIDI transmit data is transferred through a 16-byte FIFO and receive data through a 16-byte FIFO. The FIFO gives the ISA interface time to respond to the asynchronous MIDI transfer rate of 31.25K baud. The Command/Status Registers occupy the same address and are used to send instructions to and receive status information from the MPU-401. Command Register, write only MPUbase+1 D7 D6 D5 D4 D3 D2 D1 D0 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 CS7-CS0 Each write to the Command/Status Register must be monitored and the appropriate acknowledge generated. Status Register, read only MPUbase+1, Default = xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 RXS TXS CS5 CS4 CS3 CS2 CS1 CS0 CS5-CS1 D0-D5 are the 6 LSBs of the last command written to this port. TXS Transmit Buffer Status Flag. 0 - Transmit buffer not full 1 - Transmit buffer full RXS Receive Buffer Status Flag 0 - Data in Receive buffer 1 - Receive buffer empty When in "UART" mode, data is received into the receive buffer FIFO and a hardware interrupt is generated. Data can be received from two sources: MIDI data via the UART serial input or acknowledge data that is the result of a write to the Command Register (MPUbase+1). The inter- rupt is cleared by a read of the MIDI Receive Port (MPUbase+0). DS213PP4 CS4237B 72 |
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Similar Description - CS4237B |
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