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CS4237B Datasheet(PDF) 65 Page - Cirrus Logic |
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CS4237B Datasheet(HTML) 65 Page - Cirrus Logic |
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65 / 114 page  Control Indirect Registers The Control Indirect registers are accessed t hr ou g h C TRL b a se+ 3 a nd CTRL ba se +4. CTRLba se +3 is th e a ddre ss register and CTRLbase+4 is the data register used to access C0 through C8 indirect registers. WSS Master Control (C0) Default = 0xxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 RWSS res res res res res res res res Reserved. Must write 0. Could read as 0 or 1. RWSS Reset WSS registers. Setting this bit forces the WSS registers to zero, then clearing this bit forces the WSS registers to their default state. Version / Chip ID (C1) Default = 11001000 D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0 CID4 CID3 CID2 CID1 CID0 CID4-CID0 Chip Identification. Distinguishes between this chip and other codec chips that support this register set. This register is identical to the WSS X25 register. 01000 - CS4237B V2-V0 Version number. As enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip. 100 - Revision A 101 - Revision B 110 - Revision C/D 111 - Revision E Address Register Name CTRLbase+3 Control Indirect Address CTRLbase+4 Control Indirect Data Table 22. Control Indirect Access Registers Index Register Name C0 WSS Master Control C1 Version / Chip ID C2 3D Space and Center C3 3D Enable C4 Consumer Serial Port Enable C5 Lower Channel Status C6 Upper Channel Status C7 Reserved C8 CS9236 Wavetable Control Table 23. Control Indirect Registers DS213PP4 CS4237B 65 |
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