ncp1271 datasheet(13/19 Pages) ONSEMI

Part #	NCP1271

Description	Soft?뭆kip Mode Standby PWM Controller with Adjustable Skip Level and External Latch

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP1271

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13

Soft−Start Operation

Figures 28 and 29 show how the soft−start feature is

included in the pulse−width modulation (PWM)

comparator. When the NCP1271 starts up, a soft−start

voltage VSS begins at 0 V. VSS increasesgradually from 0 V

to 1.0 V in 4.0 ms and stays at 1.0 V afterward. This voltage

VSS is compared with the divided−by−3 feedback pin

voltage (VFB/3). The lesser of VSSand (VFB/3) becomes the

modulation voltage VPWM in the PWM duty cycle

generation. Initially, (VFB/3) is above 1.0 V because the

output voltage is low. As a result, VPWM is limited by the

soft start function and slowly ramps up the duty cycle (and

therefore the primary current) for the initial 4.0 ms. This

provides a greatly reduced stress on the power devices

during startup.

Figure 28. VPWM is the lesser of VSS and (VFB/3)

0

1

−

+

VSS

V / 3

FB

VPWM

Figure 29. Soft−Start (Time = 0 at VCC = VCC(on))

time

1 V

4 ms

1 V

4 ms

time must be less than130 ms

to prevent fault condition

time

4 ms

Feedback pin voltage divided−by−3, VFB/3

Pulse Width Modulation voltage, VPWM

Drain Current, ID

Soft−start voltage, VSS

Current−Mode Pulse−Width Modulation

The NCP1271 uses a current−mode fixed−frequency

PWM with internal ramp compensation. A pair of current

sense resistors RCS and Rramp sense the flyback drain

current ID. As the drain current ramps up through the

inductor and current sense resistor, a corresponding voltage

ramp is placed on the CS pin (pin 3). This voltage ranges

from very low to as high as the modulation voltage VPWM

(maximum of 1.0 V) before turning the drive off. If the

internal current ramp is ignored (i.e., Rramp ≈ 0) then the

maximum possible drain current ID(max) is shown in

Equation 2. This sets the primary current limit on a cycle

by cycle basis.

ID(max) +

1V

RCS

(eq. 2)

Figure 30. Current−Mode Implementation

LEB

CS

PWM

Output

180ns

3

Vbulk

Rramp

(1V max. signal)

VPWM

Q

S

VCS

Clock

1

0

RCS

ID

80%

max duty

Iramp

R

Figure 31. Current−Mode Timing Diagram

PWM

Output

VPWM

CS

clock

V

The timing diagram of the PWM is in Figure 31. An

internal clock turns the Drive Output (Pin 5) high in each

switching cycle. The Drive Output goes low when the CS

(Pin 3) voltage VCS intersects with the modulation voltage

VPWM. This generates the pulse width (or duty cycle). The

maximum duty cycle is limited to 80% (typically) in the

output RS latch.

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NCP1271 Datasheet(PDF) 13 Page - ON Semiconductor

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