NCP1271

http://onsemi.com

4

Figure 2. Functional Block Diagram

−

LEB

Skip/ latch

CS

FB

7.5% Jittering

65, 100 kHz

Oscillator

130ms

delay

HV

S

R

Drv

Gnd

PWM

skip

OR

4.8 V

8 V

Max duty

R

S

= 80%

180 ns

0

&

+

−

+

−

+

−

+

soft−skip

8

2

3

4

1

6

5

latch−off, reset

when Vcc < 4V

jittered ramp

current source

I

V

short

circuit

fault

12.6/

5.8 V

9.1 V

turn off

UVLO

−

+

−

+

turn on internal bias

4.1 mA when Vcc > 0.6 V

driver:

+500 mA

/ −800 mA

10V

disable

soft

skip

skip

&

double

hiccup

S

Q

10V

10V

20V

0

100uA

0.2 mA when Vcc < 0.6 V

Soft start/ soft−skip

management

−

TLD

+

soft

start

2.85 V

1 / 3

13 us filter

1

0

skip

4 ms/ 300 us

(1V max)

16.7k

75.3k

V

/ 3

FB

Q

R

Q

B2

Counter

1

PIN FUNCTION DESCRIPTION

Pin No.

Symbol

Function

Description

1

Skip/latch

Skip Adjust or

Latchoff

A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is

pulled higher than 8.0 V (typical), the controller latches off the drive.

2

FB

Feedback

An optocoupler collector pulls this pin low during regulation. If this voltage is less than

the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this

pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.

3

CS

Current Sense

This pin senses the primary current for PWM regulation. The maximum primary current

for improved stability.

4

Gnd

IC Ground

−

5

Drv

Driver Output

The NCP1271’s powerful output is capable of driving the gates of large Qg MOSFETs.

6

Supply Voltage

This is the positive supply of the device. The operating range is between 10 V (min) and

20 V (max) with a UVLO start threshold 12.6 V (typ).

8

HV

High Voltage

This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)