NCP1271 datasheet(14/19 Pages) ONSEMI

Part #	NCP1271

Description	Soft?뭆kip Mode Standby PWM Controller with Adjustable Skip Level and External Latch

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP1271

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14

Ramp Compensation

Ramp compensation is a known mean to cure

subharmonic oscillations. These oscillations take place at

half the switching frequency and occur only during

continuous conduction mode (CCM) with a duty−cycle

greater than 50%. To lower the current loop gain, one

usually injects between 50 and 75% of the inductor down

slope. The NCP1271 generates an internal current ramp

that is synchronized with the clock. This current ramp is

then routed to the CS pin. Figures 32 and 33 depict how the

ramp is generated and utilized. Ramp compensation is

simply formed by placing a resistor, Rramp, between the CS

pin and the sense resistor.

Figure 32. Internal Ramp Current Source

Ramp current, I

0

100uA

time

80% of period

ramp

100% of period

Figure 33. Inserting a Resistor in Series with the

Current Sense Information brings Ramp Compensation

Clock

Current

Ramp

Oscillator

DRIVE

CS

Rramp

Rsense

100 mA Peak

For the NCP1271, the current ramp features a swing of

100

mA. Over a 65 kHz frequency with an 80% max duty

cycle, that corresponds to an 8.1

mA/ms ramp. For a typical

flyback design, let’s assume that the primary inductance

(Lp) is 350

mH, the SMPS output is 19 V, the Vf of the

output diode is 1 V and the Np:Ns ratio is 10:1. The OFF

time primary current slope is given by:

(eq. 3)

(Vout ) Vf) @

Np

Ns

Lp

+ 571 V mH + 571 mA ms

When projected over an Rsense of 0.1

W (for example),

this becomes or 57 mV/

ms. If we select 75% of the

downslope as the required amount of ramp compensation,

then we shall inject 43 mV/

ms. Therefore, Rramp is simply

equal to:

(eq. 4)

Rramp +

43 mV ms

8.1 mA ms +

5.3 kW

It is recommended that the value of Rramp be limited to

less then 10 k

W. Values larger than this will begin to limit

the effective duty cycle of the controller and may result in

reduced transient response.

Frequency Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCP1271 switching frequency

ranges from +7.5% to −7.5% of the switching frequency in

a linear ramp with a typical period of 6 ms. Figure 34

demonstrates how the oscillation frequency changes.

Figure 34. Frequency Jittering

(The values are for the 100 kHz frequency option)

time

Oscillator Frequency

92.5 kHz

107.5 kHz

100 kHz

6 ms

Fault Detection

Figure 35 details the timer−based fault detection

circuitry. When an overload (or short circuit) event occurs,

the output voltage collapses and the optocoupler does not

conduct current. This opens the FB pin (pin 2) and VFB is

internally pulled higher than 3.0 V. Since (VFB/3) is greater

than 1 V, the controller activates an error flag and starts a

130 ms timer. If the output recovers during this time, the

timer is reset and the device continues to operate normally.

However, if the fault lasts for more than 130 ms, then the

driver turns off and the device enters the VCC Double

Hiccup mode discussed earlier. At the end of the double

hiccup, the controller tries to restart the application.

Figure 35. Block Diagram of Timer−Based Fault

Detection

Softstart

FB

130ms

delay

1V max

Fault

&

−

+

2

VSS

VFB

disable Drv

VFB

3

4.8V

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